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| 型號： | RH80530NZ006256 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 478PIN |陶瓷 |
| 文件頁數(shù)： | 50/89頁 |
| 文件大小： | 1672K |
| 代理商： | RH80530NZ006256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
50
Datasheet
298340-002
4.
System Signal Simulations
Systems must be simulated using IBIS models to determine if they are compliant with this
specification. All references to BCLK signal quality also apply to BCLK# for Differential Clocking.
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality Specifications
Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit Figure
Notes
V1
V
IL,BCLK
-0.2
0.35
V
7
Note 1
V2
V
IH,BCLK
0.92
1.45
V
7
Note 1
V3
V
IN
Absolute Voltage Range -0.2
1.45
V
7
Undershoot/Overshoot, Note 2
V4
BCLK Rising Edge
Ringback
0.35
V
8
Note 3
V5
BCLK Falling Edge
Ringback
-0.35
V
8
Note 3
V
BCLK_DPSLP
BCLK Voltage in Deep
Sleep State
0.4
1.45
V
Note 4
V
BCLK#_DPSLP
BCLK# Voltage in Deep
Sleep State
0
V
BCLK_DPSLP
- 0.2V
V
Note 4
NOTES:
1.
The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK .
2.
These specifications apply only when BCLK, BCLK# are running.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage the
differential waveform can go to after passing the VIH_DIFF (rising) or VIL_DIFF (falling) levels. VIL_DIFF (max)
= -0.57V, VIH_DIFF (min) = 0.57V.
4.
Applies when BCLK and BCLK# are stopped in Deep Sleep State.
Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
V1
V
IL,BCLK
0.3
V
20
Note 1
V2
V
IH,BCLK
2.2
V
20
Note 1
V3
V
IN
Absolute Voltage Range
-0.5
3.1
V
20
Undershoot/Overshoot, Note 2
V4
BCLK Rising Edge Ringback
2.0
V
20
Absolute Value, Note 3
V5
NOTES:
1.
The clock must rise/fall monotonically between V
IL,BCLK
and V
IH,BCLK
. BCLK must be stopped in the low state.
2.
These specifications apply only when BCLK is running. BCLK may not be above V
IH,BCLK,max
or below V
IL,
BCLK,min
for more than 50% of the clock cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can go to after passing the V
IH,BCLK
(rising) or V
IL,BCLK
(falling) voltage limits.
BCLK Falling Edge Ringback
0.5
V
20
Absolute Value, Note 3
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| RH80530NZ009256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
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