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參數(shù)資料
| 型號： | RH80530NZ006256 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 478PIN |陶瓷 |
| 文件頁數(shù)： | 39/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RH80530NZ006256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
39
Table 25. Reset Configuration AC Specifications and Power On/Power Down Timings
Symbol
Parameter
Min Typ Max
Unit
Figure
Notes
T16
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Setup
Time
4
BCLKs 11
Before deassertion of
RESET#
T17
Reset Configuration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0) Hold Time
2
20
BCLKs 11
After clock that
deasserts RESET#
T18
RESET#/PWRGOOD Setup Time
1
ms
12
Before deassertion of
RESET#
T18A
VCCT to VTTPWRGD Setup Time
1
ms
12
T18B
VCC to PWRGOOD Setup Time
10
ms
12
T18C
BSEL, VID valid time before VTTPWRGD
assertion
1
μ
s
12
T18D
RESET# inactive to Valid Outputs
1
BCLK 11
T18E
RESET# inactive to Drive Signals
4
BCLKs 11
T19A
Time from VCC(nominal)-12% to PWRGOOD
low
0
ns
13
VCC(nominal) is the VID
voltage setting
T19B
All outputs valid after PWRGOOD low
0
ns
13
T19C
All inputs required valid after PWRGOOD low 0
ns
13
T20A
Time from VCCT-12% to VTTPWRGD low
0
ns
14
T20B
All outputs valid after VTTPWRGD low
0
ns
14
T20C
All inputs required valid after VTTPWRGD low 0
ns
14
T20D
VID, BSEL signals valid after VTTPWRGD
low
0
ns
14
NOTE:
At least 1 ms must pass after PWRGOOD rises above V
IH18min
and BCLK, BCLK# meet their AC timing
specification until RESET# may be deasserted.
Table 26. APIC Bus Signal AC Specifications
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T21
PICCLK Frequency
2
33.3
MHz
Note 2
T22
PICCLK Period
30
500
ns
6
T23
PICCLK High Time
10.5
ns
6
at>1.6V
T24
PICCLK Low Time
10.5
ns
6
at<0.4V
T25
PICCLK Rise Time
0.25
3.0
ns
6
(0.4V – 1.6V)
T26
PICCLK Fall Time
0.25
3.0
ns
6
(1.6V – 0.4V)
T27
PICD[1:0] Setup Time
8.0
ns
9
Note 3
T28
PICD[1:0] Hold Time
2.5
ns
9
Note 3
T29
PICD[1:0] Valid Delay (Rising
Edge)
PICD[1:0] Valid Delay (Falling
Edge)
1.5
1.5
8.7
12.0
ns
8
Notes 3, 4
NOTES:
1.
All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.0V. All CMOS signals are
referenced at 1.0V.
2.
The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset Referenced to PICCLK Rising Edge.
3.
For Open-drain signals, Valid Delay is synonymous with Float Delay.
4.
Valid delay timings for these signals are specified into 150
to 1.5V and 0 pF of external load. For real system
timings these specifications must be derated for external capacitance at 105 ps/pF.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RH80530NZ009256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ012256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| RH80530WZ004256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80530WZ006256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
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