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| 型號(hào)： | RH80530NZ006256 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 478PIN |陶瓷 |
| 文件頁(yè)數(shù)： | 15/89頁(yè) |
| 文件大?。?/td> | 1672K |
| 代理商： | RH80530NZ006256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
15
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to the
Quick Start state. Deasserting STPCLK# will cause the processor to return to the Auto Halt state
without issuing a new Halt bus cycle.
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the
Intel
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide
for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have been
flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in
the A20M# and PREQ# signals are recognized while in the Auto Halt state.
Figure 1. Clock Control States
Quick Start
Normal
HS=false
Deep Sleep
2
HALT/Grant
Snoop
Auto Halt
HS=true
Deeper
Sleep
STPCLK#
1
BCLK stopped
or DPSLP#
snoop
occurs
BCLK on
and !DPSLP#
(!STPCLK# and !HS)
or RESET#
snoop
serviced
HLT
instruction
1
snoop
serviced
snoop
occurs
core
voltage
raised
core
voltage
reduced
STPCLK#
1
!STPCLK#
and HS
halt
break
V0001-02
NOTES
:
1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes
Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
HLT – HLT instruction executed
HS – Processor Halt State
2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description
for details.
2.2.4
Quick Start State
The processor is required to be configured for the Quick Start state by strapping the A15# signal low.
More details are provided in Section 7.1. In the Quick Start state the processor is only capable of acting
on snoop transactions generated by the system bus priority device. Because of its snooping behavior,
Quick Start can only be used in a uniprocessor (UP) configuration.
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相關(guān)代理商/技術(shù)參數(shù) |
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| RH80530NZ009256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC |
| RH80530NZ012256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80530NZ014256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80530WZ004256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80530WZ006256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
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