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參數(shù)資料
| 型號(hào)： | RD28F6408W30T70 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA80 |
| 封裝： | 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80 |
| 文件頁數(shù)： | 25/82頁 |
| 文件大?。?/td> | 749K |
| 代理商： | RD28F6408W30T70 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
19
In synchronous mode, WAIT is active when CE# is asserted. The WAIT signal is asserted if a
burst-mode read is misaligned to a 4-word boundary. By misaligned, we imply that the address
must be on a mod-4 boundary; such as xx00h, xx04h, xx08h or xx0Ch. If the address is aligned to
a 4-word boundary, the
“
delay
”
will never be seen. Also, a
“
delay
”
will only occur once per burst-
mode read sequence. When a misaligned burst-mode read crosses a 16-word boundary, the device
must deselect one row in order to select the next row. It is this selecting/de-selecting (or energizing/
de-energizing) of memory rows that causes the device to
“
delay
”
output data. It is the assertion of
the WAIT signal that informs the interfacing processor of this pending flash
“
delay.
”
During the
“
delay,
”
subsequent data reads are prohibited.
The WAIT signal is asserted depending on the burst starting address and latency count. If the
starting address is aligned to the 4-word boundary, a delay will not occur. If the starting address is
aligned to the end of a 4-word boundary, a delay equal to one clock cycle less than the latency
count will occur (worst case scenario). See
Table 9,
“
WAIT Delay
”
on page 19
. If the starting
address falls between, the delay will be dependent upon the latency count value and the starting
address as indicated in
Table 9
.
In 4- and 8-word burst modes with burst wrap enabled, the device will not assert the WAIT signal.
However, with the burst wrap disabled, the flash device will assert the WAIT signal if a burst-mode
read is misaligned and crosses a 16-word boundary. With wrap disabled, the burst mode will read 4
or 8 consecutive words based on the initial address. If the initial address is aligned on a mod-4
boundary, the WAIT signal will not be asserted. However, if the initial address is misaligned on a
mod-4 boundary and crosses the 16-word boundary limit, the WAIT signal will be asserted.
In continuous-word burst mode, the burst wrap feature does not apply and the WAIT signal is only
asserted on the first 16-word boundary crossing. The WAIT signal is inactive or at a High-Z state
when accessing register information.
Table 9. WAIT Delay
4.2.7
Burst Sequence (BS)
CR.7 sets the burst sequence. The burst sequence determines the 4- or 8-word output order. In 4- or
8-word burst modes, the burst sequence is defined as either linear or Intel. In continuous burst
mode, the burst sequence is always linear. The burst sequence depends on the interfacing
processor
’
s characteristics.
Starting Burst Address
WAIT Delay in Clock Cycles After
Crossing 16-Word Boundary
4-Word Boundary
xx0h, xx4h, xx8h, xxCh
No Delay
Start of Boundary
xx1h, xx5h, xx9h, xxDh
LC - 3
xx2h, xx6h, xxAh, xxEh
LC - 2
xx3h, xx7h, xxBh, xxFh
LC - 1
End of Boundary
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