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參數(shù)資料
| 型號： | RC28F128P33T85 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 8M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封裝： | BGA-64 |
| 文件頁數(shù)： | 39/96頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | RC28F128P33T85 |
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Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
44
Order Number: 314749-05
9.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
9.5
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated
and the memory contents at the aborted location (for a program) or block (for an
erase) are no longer valid, because the data may have been only partially written or
erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 7.0, “AC Characteristics” on page 29 for details
about signal-timing.
9.6
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 23, “Command Bus Cycles” on page 45. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| RC28F128P33T85A | 功能描述:IC FLASH 128MBIT 85NS 64EZBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| RC28F128P33TF60 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx?? P33-65nm Flash Memory |
| RC28F128P33TF60A | 功能描述:IC FLASH 128MBIT 85NS 64EZBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x20） 包裝:托盤 |
| RC28F128P3GB850 | 制造商:Micron Technology Inc 功能描述:128MB, KEARNY EBGA 3.0 - Trays |
| RC28F128P3GT850 | 制造商:Micron Technology Inc 功能描述:128MB, KEARNY EBGA 3.0 - Trays |
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