參數(shù)資料
型號： R5F56218BDLE#U0
廠商： Renesas Electronics America
文件頁數(shù)： 72/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 145TFLGA
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 103
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 145-TFLGA
包裝： 托盤
R01DS0052EJ0130 Rev.1.30
Page 3 of 147
2012.01.11
RX62N Group, RX621 Group
1. Overview
Interrupt
Interrupt control unit
Peripheral function interrupts: 146 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltage-
monitoring interrupt)
Sixteen levels specifiable for the order of priority
User break controller
(as an optional
function)
Two breakpoint channels
Address breaks in fetch cycles are specifiable (enabling ROM correction)
External bus extension
The external address space can be divided into nine areas (CS0 to CS7, SDCS), each
with independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)
A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space (however, only 176-pin
versions support 32-bit bus spaces).
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate buses
Wait control
Write buffer facility
DMA
DMA controller
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
EXDMA controller
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer
Single-address transfer enabled with the EDACK signal
Capable of direct data transfer to TFT LCD panels
Activation sources: Software trigger, external DMA transfer requests (EDREQ), and
interrupt requests from peripheral functions
Data transfer
controller
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts and interrupt requests from
peripheral functions
I/O ports
Programmable I/O
ports
I/O ports for the 176-pin LFBGA/145-pin TFLGA/144-pin LQFP/100-pin LQFP/85-pin
TFLGA
I/O pins: 126/103/103/72/58
Input pins: 2/2/2/2/2
Pull-up resistors: 56/44/44/40/28
Open-drain outputs: 35/33/33/27/23
5-V tolerance: 11/11/11/7/6
Timers
Multi-function timer
pulse unit
(16 bits x 6 channels) x 2 units
Time bases for the 12 16-bit timer channels can be provided via up to 32 pulse-input/
output lines and six pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Port output enable
Controls the high-impedance state of the MTU’s waveform output pins
Table 1.1
Outline of Specifications (2 / 4)
Classification
Module/Function
Description
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