參數(shù)資料
型號(hào)： R5F56218BDLE#U0
廠商： Renesas Electronics America
文件頁數(shù)： 122/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 145TFLGA
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 103
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 145-TFLGA
包裝： 托盤
2004 Microchip Technology Inc.
DS39609B-page 73
PIC18F6520/8520/6620/8620/6720/8720
6.2
16-bit Mode
The External
Memory Interface implemented
in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
16-bit Byte Write
16-bit Word Write
16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are
available on the External Memory Interface bus.
Following the address latch, the Output Enable signal
(OE) will enable both bytes of program memory at once
to form a 16-bit instruction word. The Chip Enable
signal (CE) is active at any time that the microcontroller
accesses external memory, whether reading or writing;
it is inactive (asserted high) whenever the device is in
Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
6.2.1
16-BIT BYTE WRITE MODE
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
FIGURE 6-1:
16-BIT BYTE WRITE MODE EXAMPLE
AD<7:0>
A<19:16>
ALE
D<15:8>
373
A<x:0>
D<7:0>
A<19:0>
A<x:0>
D<7:0>
373
OE
WRH
OE
WR(1)
CE
Note 1:
This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
WRL
D<7:0>
(LSB)
(MSB)
PIC18F8X20
D<7:0>
AD<15:8>
Address Bus
Data Bus
Control Lines
CE
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