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參數(shù)資料
| 型號(hào)： | R1LP0408CSP-5SC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 94K |
| 代理商： | R1LP0408CSP-5SC |
R1LP0408C-C Series
Rev.2.00, May.26.2004, page 8 of 12
Write Cycle
R1LP0408C-C
-5SC
-7LC
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
55
70
ns
Chip selection to end of write
tCW
50
60
ns
4
Address setup time
tAS
0
0
ns
5
Address valid to end of write
tAW
50
60
ns
Write pulse width
tWP
40
50
ns
3, 12
Write recovery time
tWR
0
0
ns
6
Write to output in high-Z
tWHZ
0
20
0
25
ns
1, 2, 7
Data to write time overlap
tDW
25
30
ns
Data hold from write time
tDH
0
0
ns
Output active from end of write
tOW
5
5
ns
2
Output disable to output in high-Z
tOHZ
0
20
0
25
ns
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS# going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP
≥ tDW min + tWHZ max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R1LP0408CSP-5SC#B0 | 功能描述:IC SRAM 4MBIT 55NS 32SOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
| R1LP0408CSP5SC#S0 | 制造商:Renesas Electronics Corporation 功能描述: |
| R1LP0408CSP-5SC#S0 | 功能描述:IC SRAM 4MBIT 55NS 32SOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| R1LP0408CSP-5SCB0 | 制造商:Renesas Electronics Corporation 功能描述:SRAM,Low Power,4Mb, x8, 55ns |
| R1LP0408CSP-5SI | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 55ns 32-Pin SOP 制造商:Renesas Electronics Corporation 功能描述:SRAM 4MBIT 5V 55NS 32SOP 制造商:Renesas Electronics Corporation 功能描述:SRAM, 4MBIT, 5V, 55NS, 32SOP 制造商:Renesas Electronics Corporation 功能描述:SRAM, 4MBIT, 5V, 55NS, 32SOP; Memory Size:4Mbit; Memory Configuration:512K x 8bit; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Memory Case Style:SOP; No. of Pins:32; Access Time:55ns; Operating Temperature Min:-40C; Operating ;RoHS Compliant: Yes |
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