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    參數(shù)資料
    型號: QLX4300SIQSR
    廠商: Intersil
    文件頁數(shù): 5/21頁
    文件大小: 0K
    描述: IC EQUALIZER REC 3.125GBPS 46QFN
    標(biāo)準(zhǔn)包裝: 100
    系列: QLx™
    應(yīng)用: 數(shù)據(jù)傳輸
    接口: SMBus(2 線/I²C)
    電源電壓: 1.1 V ~ 1.3 V
    封裝/外殼: 46-WFQFN 裸露焊盤
    供應(yīng)商設(shè)備封裝: 46-TQFN
    包裝: 帶卷 (TR)
    安裝類型: 表面貼裝
    13
    FN6982.1
    November 19, 2009
    Equalization Boost Level
    Channel equalization for the QLx4300-S45 can be
    individually set to either (a) one of 18 levels through the
    DC voltages on external control pins or (b) one of 32
    levels via a set of registers programmed by a low speed
    serial bus. The pins used to control the boost level are
    highlighted in Figure 21. Descriptions of these pins are
    listed in Table 1. Please refer to “Pin Descrptions” on
    page 3 for descriptions of all other pins on the
    QLx4300-S45.
    The boost setting for equalizer channel k can be read as
    a three digit ternary number across CP[k][A,B,C]. The
    ternary value is established by the value of the resistor
    between VDD and the CP[k][A,B,C] pin.
    As a second option, the equalizer boost setting can be
    taken from a set of registers programmed through a
    serial bus interface (pins 16, 17, 45, and 46). Using this
    interface, a set of registers is programmed to store the
    boost level. A total of 21 registers are used. Registers 2
    through 21 are parsed into four 5-bit words. Each 5-bit
    word determines which of 32 boost levels to use for the
    corresponding equalizer. Register 1 instructs the
    QLx4300-S45 to use registers 2 through 21 to set the
    boost level rather than the control pins CP[k][A,B,C].
    Both options have their relative advantages. The control
    pin option minimizes the need for external controllers as
    the boost level can be set in the board design resulting in
    a compact layout. The register option is more flexible for
    cases in which the optimum boost level will not be known
    and can be changed by a host bus adapter with a small
    number of pins. It is noted that the serial bus interface
    can also be daisy-chained among multiple QLx4300-S45
    devices to afford a compact programmable solution even
    when a large number of data lines need to be equalized.
    Upon power-up, the default value of all the registers (and
    register 1 in particular) is zero, and thus, the CP pins are
    used to set the boost level. This permits an alternate
    interpretation on setting the boost level. Specifically, the
    CP pins define the default boost level until the registers
    are (if ever) programmed via the serial bus.
    Control Pin Boost Setting
    When register 1 of the QLx4300-S45 is zero (the default
    state on power-up), the voltages at the CP pins are used
    to determine the boost level of each channel. For each of
    the four channels, k, the [A], [B], and [C] control pins
    (CP[k]) are associated with a 3-bit non binary word.
    While [A] can take one of two values, ‘LOW’ or ‘HIGH’,
    [B] and [C] can take one of three different values: ‘LOW’,
    ‘MIDDLE’, or ‘HIGH’. This is achieved by changing the
    value of a resistor connected between VDD and the CP
    pin, which is internally pulled low with a 25kΩ resistor.
    Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,
    ‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is
    achieved with an open resistance. Table 2 defines the
    mapping from the 3-bit CP word to the 18 out of 32
    possible levels available via the serial interface.
    If all four channels are to use the same boost level, then
    a minimum number of board resistors can be realized by
    tying together like CP[k][A,B,C] pins across all channels
    k. For instance, all four CP[k][A] pins can be tied to the
    same resistor running to VDD. Consequently, only three
    resistors are needed to control the boost of all four
    channels. If the CP Pins are tied together and the 25kΩ is
    used, the value changes to a 6.25kΩ resistor because the
    25kΩ is divided by 4.
    TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR
    AND PROGRAMMED BOOST LEVELS
    RESISTANCE BETWEEN CP PIN AND VDD
    SERIAL
    BOOST LEVEL
    CP[A]
    CP[B]
    CP[C]
    Open
    0
    Open
    25kΩ
    2
    Open
    4
    Open
    25kΩ
    Open
    6
    Open
    25kΩ
    8
    Open
    25kΩ
    10
    Open
    Open
    12
    Open
    25kΩ
    14
    Open
    15
    Open
    16
    Open
    25kΩ
    17
    Open
    19
    25kΩ
    Open
    21
    25kΩ
    23
    25kΩ
    24
    Open
    26
    25kΩ
    28
    31
    QLx4300-S45
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