FN6982.1 November 19, 2009 OUT2[N,P] 33, 34 Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz" />
參數資料
型號: QLX4300SIQSR
廠商: Intersil
文件頁數: 16/21頁
文件大?。?/td> 0K
描述: IC EQUALIZER REC 3.125GBPS 46QFN
標準包裝: 100
系列: QLx™
應用: 數據傳輸
接口: SMBus(2 線/I²C)
電源電壓: 1.1 V ~ 1.3 V
封裝/外殼: 46-WFQFN 裸露焊盤
供應商設備封裝: 46-TQFN
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
4
FN6982.1
November 19, 2009
OUT2[N,P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT1[N,P]
36, 37
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
BGREF
38
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and
CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI
is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and
20MHz. Internally pulled down.
EXPOSED
PAD
-
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
Pin Descrptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
QLx4300-S45
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