FN6982.1 November 19, 2009 the boost level and one of 18 compensation levels when the CP[k] pins are used to set the level. The equalizer trans" />
參數(shù)資料
型號(hào)： QLX4300SIQSR
廠商： Intersil
文件頁(yè)數(shù)： 3/21頁(yè)
文件大小： 0K
描述： IC EQUALIZER REC 3.125GBPS 46QFN
標(biāo)準(zhǔn)包裝： 100
系列： QLx™
應(yīng)用： 數(shù)據(jù)傳輸
接口： SMBus（2 線/I²C）
電源電壓： 1.1 V ~ 1.3 V
封裝/外殼： 46-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 46-TQFN
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
11
FN6982.1
November 19, 2009
the boost level and one of 18 compensation levels when
the CP[k] pins are used to set the level. The equalizer
transfer functions for a subset of these compensation
levels are plotted in Figure 18. The flexibility of this
adjustable compensation architecture enables signal
fidelity to be optimized on a channel-by-channel basis,
providing support for a wide variety of channel
characteristics and data rates ranging from 2.5Gb/s to
3.125Gb/s. Because the boost level is externally set
rather than internally adapted, the QLx4300-S45
provides reliable communication from the very first bit
transmitted. There is no time needed for adaptation and
control loop convergence. Furthermore, there are no
pathological data patterns that will cause the
QLx4300-S45 to move to an incorrect boost level.
The “Applications Information” section beginning on
page 12 details how to set the boost level by both the
CP-pin voltage approach and the serial programming
approach.
CML Input and Output Buffers
The input and output buffers for the high-speed data
channels in the QLx4300-S45 are implemented using
CML. Equivalent input and output circuits are shown in
Figures 19 and 20, respectively.
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx4300-S45 contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by
measuring the amplitude of the equalized signal and
comparing that to a threshold set by the current at the
DT pin. When the amplitude falls below the threshold,
the output driver stages are muted and held at their
nominal common mode voltage1.
FIGURE 18. EQUALIZER TRANSFER FUNCTIONS FOR
SETTINGS 0, 5, 10, 15, 20, 25, AND 31 IN
THE QLx4300-S45
FIGURE 19. CML INPUT EQUIVALENT CIRCUIT FOR THE
QLx4300-S45
FIGURE 20. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx4300-S45
NOTE: The load value of 52Ω is used to internally match
SDD22 for a characteristic impedance of 50Ω.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
IN[k] P
IN[k] N
Buffer
VDD
50
VDD
52
OUT[k] P
OUT[k] N
QLx4300-S45
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