FN6982.1 November 19, 2009 Input Return Loss (Com. to Diff. Conversion) SDC11
參數(shù)資料
型號(hào): QLX4300SIQSR
廠商: Intersil
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 0K
描述: IC EQUALIZER REC 3.125GBPS 46QFN
標(biāo)準(zhǔn)包裝: 100
系列: QLx™
應(yīng)用: 數(shù)據(jù)傳輸
接口: SMBus(2 線/I²C)
電源電壓: 1.1 V ~ 1.3 V
封裝/外殼: 46-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 46-TQFN
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
6
FN6982.1
November 19, 2009
Input Return Loss
(Com. to Diff. Conversion)
SDC11
50MHz to 3.75GHz
20
dB
Output Amplitude Range
VOUT
Active data transmission mode; Measured
differentially at OUT[k]P and OUT[k]N with
50Ω load on both output pins
450
550
650
mVP-P
Line Silence mode; Measured differentially
at OUT[k]P and OUT[k]N with 50Ω load on
both output pins
10
20
mVP-P
Differential Output
Impedance
Measured on OUT[k]
80
105
120
Ω
Output Return Loss
(Differential)
SDD22
50MHz to 3.75GHz
10
dB
Output Return Loss
(Common Mode)
SCC22
50MHz to 3.75GHz
5
dB
Output Return Loss (Com.
to Diff. Conversion)
SDC22
50MHz to 3.75GHz
20
dB
Output Residual Jitter
3.125Gb/s; Up to 20m 24AWG standard
twin-axial cable (approx. -25dB @
2.5GHz); 800mVP-P ≤ VIN ≤ 1600mVP-P
0.15
0.25
UI
Output Transition Time
tr, tf
20% to 80%
306080
ps
Lane-to-Lane Skew
50
ps
Propagation Delay
From IN[k] to OUT[k]
500
ps
Data-to-Line Silence
Response Time
tDS
Time to transition from active data to line
silence (muted output) on 20m 24AWG
standard twin-axial cable at 3.125Gb/s
15
ns
Time from last bit of ALIGN(0) for SAS OOB
signaling to line silence (<20mVP-P
output); Meritec 24AWG 20m; 3.125Gb/s
14
ns
Line Silence-to-Data
Response Time
tSD
Time to transition from line silence mode
(muted output) to active data on 20m
24AWG standard twin-axial cable at
3.125Gb/s
20
ns
Time from first bit of ALIGN(0) for SAS
OOB signaling to 450mVP-P output;
Meritec 24AWG 20m; 3.125Gb/s
19
ns
Timing Difference (SAS)
|tDS - tSD| For SAS OOB signaling support; Meritec
24AWG 20m
5ns
NOTES:
3. After channel loss, differential amplitudes at QLx4300-S45 inputs must meet the input voltage range specified in “Absolute
4. Temperature = +25°C, VDD = 1.2V.
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
6. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
9. Measured differentially across the data source.
Electrical Specifications Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
PARAMETERS
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS NOTES
QLx4300-S45
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