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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 83/162頁(yè) |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
86
PM2329 ClassiPI Network Classification Processor Datasheet
Rule memory write or read operation can be performed either in random access mode or in sequential
access mode. In general, the processor should set up the Rule Indirect Command Register to specify the
auto-increment mode, etc. It should then set up the address of the location or the starting address of the
block of locations to be accessed. It can then access the addressed location or access sequential location
depending on the programming of the auto-increment bit.
Note that read or write operations are performed internally when the trigger word is accessed as explained
below. However, if the RIAR, RICR or RIDR have not been written to since the last rule memory access,
an internal read to the rule memory is not performed since the current RIDR content correctly reflects the
address rule memory content.
During random reads, the processor must perform a dummy read (and discard the value read back) to
trigger the actual read internally, and then perform a second read to get the real data. For sequential reads,
only one (the first) dummy read is required for each block of data read sequentially. In either case, the first
dummy read needs to be performed to the trigger word only.
During writes, processor can simply write to the Indirect Data Register and the device will execute the
internal write cycle when the trigger word is written. There are no dummy writes to be performed,
however, the processor must ensure that all the enabled data words are written to first, before the trigger
word is written.
As long as the processor manages rule memory Write and Read operations using the RSR handshake, the
processor can perform these operations at any time even when OC sequencing is in progress--the read or
write operation will take place arbitrated by PM2329 control logic. The software must ensure coherency of
OC operation vs. its access operation. Also, it must manage multiple rule word updates using the RSR bit.
Note that all the rules in the rule memory are initialized to NO MATCH after the BIST sequence is
completed successfully; control software need not initialize unused rules.
Rule Updates when PM2329 is processing an OC
When an OC is in progress, rule update for all columns that are in the partition of the current OC is
deferred until the last result of the OC has been transferred out of the processing engine to the result FIFO.
This update deferral includes times when the processing engine has stalled if the Result FIFO is full, in
other words, the update will not occur during processing engine stalls.
Note that these columns can contain rules that belong to the current partition (as defined by the RSA and
REA fields) and those that do not belong to the current partition--none of the rules in these columns will be
updated until the condition stated above occurs.
Columns that are not participating in the current OC can be updated at all times. However, note if a rule
update is started that results in update deferral (since it belongs to a column of the current partition), the
RSR handshake control will prevent loading of a new rule to be updated that could otherwise be updated
(one that does not belong to a column of the current partition).
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