參數(shù)資料
型號: PIC16C662T-20I/P
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù): 95/136頁
文件大?。?/td> 634K
代理商: PIC16C662T-20I/P
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 61
PIC16C64X & PIC16C66X
9.4.5
PARITY ERROR RESET (PER)
PIC16C64X & PIC16C66X devices have on-chip parity
bits that can be used to verify the contents of program
memory. Parity bits may be useful in applications in
order to increase overall reliability of a system.
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
a program executes, the parity is veried. The even
parity bit is XOR’d with the even bits in the program
memory word. The odd parity bit is negated and XOR’d
with the odd bits in the program memory word. When
an error is detected, a reset is generated and the PER
ag bit in the PCON register is set. This indication can
allow software to act on a failure. However, there is no
indication of the program memory location of the failure
of the Program Memory. This ag can only be cleared
in software or by a POR.
The parity array is user selectable during programming.
Bit7 of the conguration word located at address 2007h
can be programmed (read as '0') to disable parity
checking. If left unprogrammed (read as '1'), parity
checking is enabled.
9.4.6
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
the OST is activated. The total time-out will vary based
on oscillator conguration and PWRTE bit status. For
example, in RC mode with the PWRTE bit set (PWRT
disabled), there will be no time-out at all. Figure 9-9,
and
depict
time-out
sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-10). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
Table 9-5 shows the reset conditions for some special
registers, while Table 9-6 shows the reset conditions
for all the registers.
9.4.7
POWER CONTROL/STATUS REGISTER
(PCON)
The power control/status register, PCON (address
8Eh) has four bits. See Figure 4-10 for register.
Bit0 is BOR (Brown-out Reset). BOR is unknown on a
Power-on-reset. It must initially be set by the user and
checked on subsequent resets to see if BOR = '0'
indicating that a Brown-out Reset has occurred. The
BOR status bit is a “don’t care” bit and is not necessar-
ily predictable if the brown-out circuit is disabled (by
clearing the BODEN bit in the Conguration word).
Bit1 is POR (Power-on Reset). It is cleared on a
Power-on Reset and is unaffected otherwise. The user
set this bit following a Power-on Reset. On subsequent
resets if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
Bit2 is PER (Parity Error Reset). It is cleared on a Parity
Error Reset and must be set by user software. It will
also be set on a Power-on Reset.
Bit7 is MPEEN (Memory Parity Error Enable). This bit
reects the status of the MPEEN bit in conguration
word. It is unaffected by any reset or interrupt.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Conguration
Power-up
Brown-out Reset
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
72 ms
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