參數(shù)資料
型號: PIC16C662T-20I/P
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù): 70/136頁
文件大?。?/td> 634K
代理商: PIC16C662T-20I/P
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 39
PIC16C64X & PIC16C66X
5.7
Parallel Slave Port
(PIC16C661 and PIC16C662 only)
PORTD operates as an 8-bit wide parallel slave port, or
as a microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through
RD control input pin (RE0/RD) and WR control input pin
(RE1/WR).
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be congured as inputs (set).
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data ow.
Input Buffer Full Status Flag bit IBF (TRISE<7>) is set
if a received word is waiting to be read by the CPU.
Once the PORTD input latch is read, bit IBF is cleared.
IBF is a read only status bit. Output Buffer Full Status
Flag bit OBF (TRISE<6>) is set if a word written to
PORTD latch is waiting to be read by the external bus.
Once the PORTD output latch is read by the micropro-
cessor, bit OBF is cleared. Input Buffer Overow Status
ag bit IBOV (TRISE<5>) is set if a second write to the
microprocessor port is attempted when the previous
word has not been read by the CPU (the rst word is
retained in the buffer).
When not in Parallel Slave Port mode, bits IBF and
OBF are held clear. However, if ag bit IBOV was pre-
viously set, it must be cleared in software.
An interrupt is generated and latched into ag bit
PSPIF (PIR1<7>) when a read or a write operation is
completed. Flag bit PSPIF must be cleared by user
software. The interrupt can be disabled by clearing the
interrupt enable bit PSPIE (PIE1<7>).
FIGURE 5-12: PORTD AND PORTE AS A
PARALLEL SLAVE PORT
Data bus
WR
PORT
RD
RDx
Q
D
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt ag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pins have protection diodes to VDD and VSS.
TTL
TABLE 5-11:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0
xxxx xxxx
uuuu uuuu
09h
PORTE
RE2
RE1
RE0
---- -xxx
---- -uuu
89h
TRISE
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
0000 -111
0Ch
PIR1
PSPIF(1)
CMIF
00-- ----
8Ch
PIE1
PSPIE(1)
CMIE
00-- ----
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.
Note 1:
These bits are reserved on the PIC16C641/642, always maintain these bits clear.
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