參數(shù)資料
型號(hào): PIC16C662T-20I/P
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù): 84/136頁
文件大?。?/td> 634K
代理商: PIC16C662T-20I/P
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 51
PIC16C64X & PIC16C66X
7.6
Comparator Interrupts
The comparator interrupt ag is set whenever there is
a change in the output value of either comparator. User
software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit (PIR1<6>), is the comparator interrupt ag
and must be cleared in user software.
To enable the Comparator interrupt the following bits
must be set:
CMIE (PIE1<6>)
PEIE (INTCON<6>)
GIE (INTCON<7>)
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
Any read or write of CMCON. This will end the
mismatch condition.
b)
Clear ag bit CMIF.
A mismatch condition will continue to set ag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow ag bit CMIF to be cleared.
7.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake up the device from SLEEP mode when enabled.
While the comparator is powered up, higher sleep
currents than shown in the power-down current
specication will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM2:CM0 = 111, before entering sleep.
If the device wakes up from sleep, the contents of the
CMCON register are not affected.
7.8
Effects of a RESET
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator
reset
mode,
CM2:CM0 = 000.
This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at reset time. The comparators will be powered
down during the reset interval.
7.9
Analog Input Connection
Considerations
A simplied circuit for an analog input is shown in
Figure 7-5. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 7-5:
ANALOG INPUT MODEL
VA
RS
AIN
CPIN
5 pF
VDD
VT = 0.6V
RC < 10k
ILEAKAGE
±500 nA
VSS
Legend CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE
= Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
RS
= Source Impedance
VA
= Analog Voltage
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