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參數(shù)資料
| 型號： | PI7C9X20404SLCFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 62/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 128LQFP |
| 標準包裝： | 90 |
| 系列： | SlimLine™ |
| 應用： | 封裝開關，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 65 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
7.2.95
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only)
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Reserved
RO
Reset to 0000h.
16
Port Arbitration
Table Status
RO
When set, it indicates that any entry of the Port Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set.
Reset to 0b.
17
VC Negotiation
Pending
RO
When set, it indicates that the VC resource is still in the process of
negotiation. This bit is cleared after the VC negotiation is complete.
Reset to 0b.
31:18
Reserved
RO
Reset to 0.
7.2.96
PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh
(Upstream Only)
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-1 Table Entry Size in 4 Bits
63 - 56
55 - 48
47 - 40
39 - 32
31 - 24
23 - 16
15 - 8
7 - 0
Byte Location
Phase
[15:14]
Phase
[13:12]
Phase
[11:10]
Phase
[9:8]
Phase
[7:6]
Phase
[5:4]
Phase
[3:2]
Phase
[1:0]
00h
Phase
[31:30]
Phase
[29:28]
Phase
[27:26]
Phase
[25:24]
Phase
[23:22]
Phase
[21:20]
Phase
[19:18]
Phase
[17:16]
08h
Phase
[47:46]
Phase
[45:44]
Phase
[43:42]
Phase
[41:40]
Phase
[39:38]
Phase
[37:36]
Phase
[35:34]
Phase
[33:32]
10h
Phase
[63:62]
Phase
[61:60]
Phase
[59:58]
Phase
[57:56]
Phase
[55:54]
Phase
[53:52]
Phase
[51:50]
Phase
[49:48]
18h
Phase
[79:78]
Phase
[77:76]
Phase
[75:74]
Phase
[73:72]
Phase
[71:70]
Phase
[69:68]
Phase
[67:66]
Phase
[65:64]
20h
Phase
[95:94]
Phase
[93:92]
Phase
[91:90]
Phase
[89:88]
Phase
[87:86]
Phase
[85:84]
Phase
[83:82]
Phase
[81:80]
28h
Phase
[111:110]
Phase
[109:108]
Phase
[107:106]
Phase
[105:104]
Phase
[103:102]
Phase
[101:100]
Phase
[99:98]
Phase
[97:96]
30h
Phase
[127:126]
Phase
[125:124]
Phase
[123:122]
Phase
[121:120]
Phase
[119:118]
Phase
[117:116]
Phase
[115:114]
Phase
[113:112]
38h
7.2.97
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Extended
Capabilities ID
RO
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
7.2.98
CAPABILITY VERSION – OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20404SLCFDEX | 功能描述:外圍驅動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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