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參數(shù)資料
| 型號： | PI7C9X20404SLCFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 45/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | SlimLine™ |
| 應(yīng)用： | 封裝開關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 5 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
3.2
PORT CONFIGURATION SIGNALS .......................................................................................................12
3.3
MISCELLANEOUS SIGNALS..................................................................................................................12
3.4
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................13
3.5
POWER PINS.............................................................................................................................................14
4
PIN ASSIGNMENTS .........................................................................................................................................15
4.1
PIN LIST OF 128-PIN LQFP.......................................................................................................................15
5
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH ....................................................................................................................................................... 19
5.6.2
PD ....................................................................................................................................................... 19
5.6.3
NPHD ................................................................................................................................................. 19
5.6.4
CPLH .................................................................................................................................................. 19
5.6.5
CPLD .................................................................................................................................................. 19
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................20
5.9
FLOW CONTROL .....................................................................................................................................21
5.10
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 22
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 22
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 24
6.2
SMBUS INTERFACE .................................................................................................................................30
7
REGISTER DESCRIPTION .............................................................................................................................31
7.1
REGISTER TYPES ....................................................................................................................................31
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS....................................................................31
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 33
7.2.2
DEVICE ID REGISTER – OFFSET 00h............................................................................................. 33
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 33
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 34
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 34
7.2.6
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 34
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch......................................................................................... 35
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相關(guān)代理商/技術(shù)參數(shù) |
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| PI7C9X20404SLCFDEX | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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