TM Family Datasheet Page 28 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào): PI7C9X20404SLCFDE
廠商: Pericom
文件頁(yè)數(shù): 21/77頁(yè)
文件大小: 0K
描述: IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝: 90
系列: SlimLine™
應(yīng)用: 封裝開(kāi)關(guān),4 端口/4 線道
接口: PCI Express
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 28 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
54h
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 2
Bit [0]: No_Soft_Reset
Power Management Capability for Port 2
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
55h
84h (Port 2)
84h: Bit [31:24]
Power Management Data for Port 2
Bit [15:8] – read only as Data register
56h
84h (Port 3)
84h: Bit [3]
80h (Port 3)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 3
Bit [0]: No_Soft_Reset
Power Management Capability for Port 3
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
57h
84h (Port 2)
84h: Bit [31:24]
Power Management Data for Port 3
Bit [15:8] – read only as Data register
60h
214h (Port 0)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 0
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
62h
214h (Port 1)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 1
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
64h
214h (Port 2)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 2
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
66h
214h (Port 3)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 3
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
70h
B0h (Port 0)
B0h – Bit [15:0]
Replay Time-out Counter for Port 0
Bit [15:0]: Relay Time-out Counter
72h
B0h (Port 1)
B0h – Bit [15:0]
Replay Time-out Counter for Port 1
Bit [15:0]: Relay Time-out Counter
74h
B0h (Port 2)
B0h – Bit [15:0]
Replay Time-out Counter for Port 2
Bit [15:0]: Relay Time-out Counter
76h
B0h (Port 3)
B0h – Bit [15:0]
Replay Time-out Counter for Port 3
Bit [15:0]: Relay Time-out Counter
80h
B0h (Port 0)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 0
Bit [31:16]: Acknowledge Latency Timer
82h
B0h (Port 1)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 1
Bit [31:16]: Acknowledge Latency Timer
84h
B0h (Port 2)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 2
Bit [31:16]: Acknowledge Latency Timer
86h
B0h (Port 3)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 3
Bit [31:16]: Acknowledge Latency Timer
90h
B4h (Port 0)
B4h: Bit [31:16]
PHY Parameter for Port 0
Bit [31:16]: PHY Parameter
92h
B4h (Port 1)
B4h: Bit [31:16]
PHY Parameter for Port 1
Bit [31:16]: PHY Parameter
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