參數資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數： | 66/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標準包裝： | 27 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應商設備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 55 of 114
DEC 2009 REVISION 1.02
For upstream transactions, when PI7C8154A detects a read data parity error on the primary bus, the
following events occur:
PI7C8154A asserts P_PERR# 2 cycles following the data transfer, if the primary interface
parity error response bit is set in the command register.
PI7C8154A sets the detected parity error bit in the primary status register.
PI7C8154A sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
PI7C8154A forwards the bad parity with the data back to the initiator on the secondary bus. If
the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus,
the data is discarded and the data with bad parity is not returned to the initiator.
PI7C8154A completes the transaction normally.
PI7C8154A returns to the initiator the data and parity that was received from the target. When the
initiator detects a parity error on this read data and is enabled to report it, the initiator asserts
PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility
for handling a parity error condition; therefore, when PI7C8154A detects PERR# asserted while
returning read data to the initiator, PI7C8154A does not take any further action and completes the
transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8154A detects a data parity error during a delayed write transaction, the initiator drives
data and data parity, and the target checks parity and conditionally asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8154A completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data,
byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When
PI7C8154A detects a parity error on the write data for the initial delayed write request transaction,
the following events occur:
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154A asserts
TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested,
STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer,
PI7C8154A also asserts PERR#.
If the parity-error-response bit is not set, PI7C8154A returns a target retry. It queues the
transaction as usual. PI7C8154A does not assert PERR#. In this case, the initiator repeats the
transaction.
PI7C8154A sets the detected-parity-error bit in the status register corresponding to the initiator
bus, regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s re-attempts of the
write transaction may not match the original queued delayed write information contained in the
delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in
a system error (P_SERR# assertion).
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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