- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 23/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標準包裝： | 27 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應商設備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 16 of 112
DEC 2009 REVISION 1.02
Name
Pin #
Type
Description
S_TRDY#
A10
STS
Secondary TRDY (Active LOW): Driven by the
target of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
S_DEVSEL#
B10
STS
Secondary Device Select (Active LOW): Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
S_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a de-
asserted state for one cycle.
S_STOP#
C10
STS
Secondary STOP (Active LOW): Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
S_LOCK#
A11
STS
Secondary LOCK (Active LOW): Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, when it is propagating a locked
transaction downstream. Bridge does not propagate
locked transactions upstream.
S_PERR#
C11
STS
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received
on the secondary interface. Before being tri-stated,
it is driven to a de-asserted state for one cycle.
S_SERR#
B11
I
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system
error condition.
S_REQ#[8:0]
E1, E3, D2, D1, E4, D3, C2,
C1, D4
I
Secondary Request (Active LOW): This is
asserted by an external device to indicate that it
wants to start a transaction on the secondary bus.
The input is externally pulled up through a resistor
to VDD.
S_GNT#[8:0]
H1, G3, G2, G4, G1, F2, F1,
F3, E2
TS
Secondary Grant (Active LOW): PI7C8154A
asserts these pins to allow external masters to access
the secondary bus. Bridge de-asserts these pins for
at least 2 PCI clock cycles before asserting it again.
During idle and S_GNT# deasserted, PI7C8154A
will drive S_AD, S_CBE, and S_PAR.
S_RESET#
H2
O
Secondary RESET (Active LOW): Asserted when
any of the following conditions are met:
1.
Signal P_RESET# is asserted.
2.
Secondary reset bit in bridge control register in
configuration space is set.
3.
The chip reset bit in the chip control register in
configuration space is set.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, S_PAR, and
S_PAR64.
S_M66EN
A14
I/OD
Secondary Interface 66MHz Operation: This
input is used to specify if bridge is capable of
running at 66MHz on the secondary side. When
HIGH, the Secondary bus may run at 66MHz.
When LOW, the Secondary bus may only run at
33MHz. If P_M66EN is pulled LOW, the
S_M66EN is driven LOW.
S_CFN#
K1
I
Secondary Bus Central Function Control Pin:
When tied LOW, it enables the internal arbiter.
When tied HIGH, an external arbiter must be used.
S_REQ#[0] is reconfigured to be the secondary bus
grant input, and S_GNT#[0] is reconfigured to be
the secondary bus request output.
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。