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參數(shù)資料
| 型號： | PI7C8150ANDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 70/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 61 of 111
APRIL 2006 – Revision 1.1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions:
PI7C8150A is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150A detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
Table 6-6. Assertion of S_PERR_L
S_PERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
0
2
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions:
PI7C8150A has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
PI7C8150A did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Table 6-7. Assertion of P_SERR_L for Data Parity Errors
P_SERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
06-0057
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
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