參數(shù)資料
型號： PI7C8150ANDE
廠商： Pericom
文件頁數(shù)： 33/111頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標準包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 28 of 111
APRIL 2006 – Revision 1.1
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C8150A imposes internal read address boundaries on read pre-fetched data. When a
read transaction reaches one of these aligned address boundaries, the PI7C8150A stops pre-
fetched data, unless the target signals a target disconnect before the read pre-fetched
boundary is reached. When PI7C8150A finishes transferring this read data to the initiator,
it returns a target disconnect with the last data transfer, unless the initiator completes the
transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is
discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flow-
through mode during read operations.
Table 3-4 shows the read pre-fetch address boundaries for read transactions during non-
flow-through mode.
Table 3-4. Read Prefetch Address Boundaries
Type of Transaction
Address Space
Cache
Line
Size
(CLS)
Prefetch
Aligned
Address
Boundary
Configuration Read
-
*
One DWORD (no prefetch)
I/O Read
-
*
One DWORD (no prefetch)
Memory Read
Non-Prefetchable
*
One DWORD (no prefetch)
Memory Read
Prefetchable
CLS = 0 or 16
16-DWORD aligned address
boundary
Memory Read
Prefetchable
CLS = 1, 2, 4, 8, 16
Cache line address boundary
Memory Read Line
-
CLS = 0 or 16
16-DWORD aligned address
boundary
Memory Read Line
-
CLS = 1, 2, 4, 8, 16
Cache line boundary
Memory Read Multiple
-
CLS = 0 or 16
32-DWORD aligned address
boundary
Memory Read Multiple
-
CLS = 1, 2, 4, 8, 16
2X of cache line boundary
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 3-5. Read Transaction Prefetching
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.
3.6.4
DELAYED READ REQUESTS
PI7C8150A treats all read transactions as delayed read transactions, which means that the
read request from the initiator is posted into a delayed transaction queue. Read data from
the target is placed in the read data queue directed toward the initiator bus interface and is
transferred to the initiator when the initiator repeats the read transaction.
06-0057
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