參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 28/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 23 of 111
APRIL 2006 – Revision 1.1
If either of the lowest two address bits is non-zero, PI7C8150A automatically disconnects
the transaction after the first data transfer.
3.3
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8150A always performs positive address decoding (medium decode) when accepting
transactions on either the primary or secondary buses. PI7C8150A never does subtractive
decode.
3.4
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases.
A data phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted.
A transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the
same PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is
de-asserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L
are asserted. See Section 3.8 for further discussion of transaction termination.
Depending on the command type, PI7C8150A can support multiple data phase
PCI transactions. For detailed descriptions of how PI7C8150A imposes disconnect
boundaries, see Section 3.5.4 for write address boundaries and Section 3.6.3 read address
boundaries.
3.5
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions.
Table 3-2 shows the method of forwarding used for each type of write operation.
Table 3-2. Write Transaction Forwarding
Type of Transaction
Type of Forwarding
Memory Write
Posted (except VGA memory)
Memory Write and Invalidate
Posted
Memory Write to VGA memory
Delayed
I/O Write
Delayed
Type 1 Configuration Write
Delayed
3.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C8150A determines that a memory write transaction is to be forwarded across
the bridge, PI7C8150A asserts DEVSEL_L with medium timing and TRDY_L
in the next cycle, provided that enough buffer space is available in the posted memory
write queue for the address and at least one DWORD of data. Under
this condition, PI7C8150A accepts write data without obtaining access to the target bus.
06-0057
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