參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 27/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 22 of 111
APRIL 2006 – Revision 1.1
3.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150A.
Table 3-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150A initiates
transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150A
responds to transactions as a target, on the primary (P) and secondary (S) buses.
Table 3-1. PCI Transactions
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
0001
Special Cycle
Y
N
0010
I/O Read
Y
0011
I/O Write
Y
0100
Reserved
N
0101
Reserved
N
0110
Memory Read
Y
0111
Memory Write
Y
1000
Reserved
N
1001
Reserved
N
1010
Configuration Read
N
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
1101
Dual Address Cycle
Y
1110
Memory Read Line
Y
1111
Memory Write and Invalidate
Y
As indicated in Table 3-1, the following PCI commands are not supported by
PI7C8150A:
PI7C8150A never initiates a PCI transaction with a reserved command code and, as
a target, PI7C8150A ignores reserved command codes.
PI7C8150A does not generate interrupt acknowledge transactions. PI7C8150A
ignores interrupt acknowledge transactions as a target.
PI7C8150A does not respond to special cycle transactions. PI7C8150A cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
PI7C8150A neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
3.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C8150A supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
06-0057
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