參數(shù)資料
型號(hào)： PDI1394P22
廠商： NXP Semiconductors N.V.
英文描述： 3-port Physical Layer Interface(三端口物理層接口)
中文描述： 三端口物理層接口（三端口物理層接口）
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 163K
代理商： PDI1394P22
Philips Semiconductors
Objective specification
PDI1394P22
3-port physical layer interface
1999 Jul 09
4
Name
Description
I/O
Pin Numbers
Pin Type
C/LKON
CMOS 5V tol
18
I/O
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10k
resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is deasserted low when
the LPS input terminal is active.
DGND
Supply
2, 14, 25, 56, 64
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
D0–D7
CMOS 5V tol
5, 6, 8, 9, 10, 11,
12, 13
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P22 and the LLC. Bus holders are built into these terminals.
DVDD
Supply
7, 17, 26, 27, 62
—
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10
μ
F filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
/ISO
CMOS
23
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P22 and LLC, the /ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the /ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5V tol
16
I
Link Power Status input. This terminal is used to monitor the power
status of the LLC, and is connected to either the V
supplying the link
layer controller through a 1k
resistor, or to a pulsed output which is
active when the LLC is powered. The pulsed output is useful when using
an isolation barrier. If this input is low for more than 25 s, the LLC is
considered powered down. If this input is high for more than 20 ns, the
LLC is considered powered up. If the LLC is powered-down, the
PHY–LLC interface is disabled, and the PDI1394P22 performs only the
basic repeater functions required for network initialization and operation.
Bus holder is built into this terminal.
LREQ
CMOS 5V tol
1
I
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P22. Bus holder is built into this terminal.
PC0, PC1,
PC2
CMOS 5V tol
20, 21, 22
I
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 18 for encoding.
PD
CMOS 5V tol
19
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. Bus holder is built into this terminal. For more information, refer to
Section 17.3
PLLGND
Supply
58
—
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLLVDD
Supply
57
—
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1
μ
F
and 0.001
μ
F. Lower frequency 10
μ
F filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
/RESET
CMOS 5V tol
61
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V
DD
is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
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PDI1394P23BD,118 功能描述:輸入/輸出控制器接口集成電路 1394 2-PORT PHY NO NEW DESIGNS RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
PDI1394P23BD,151 功能描述:輸入/輸出控制器接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
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