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參數(shù)資料
| 型號： | PCE84C882 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller for monitor OSD and auto-sync applications(監(jiān)視器屏幕顯示和自動同步應(yīng)用的微控制器) |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 45/60頁 |
| 文件大?。?/td> | 409K |
| 代理商： | PCE84C882 |
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1996 Jan 08
45
Philips Semiconductors
Preliminary specification
Microcontroller for monitor OSD
and auto-sync applications
PCE84C882
15 8-BIT COUNTER (T3)
One application for this counter is in the frequency
measurement of the Hsync signal.
The block diagram of the 8-bit counter is shown in Fig.33.
A Schmitt trigger is used at the input for noise rejection and
also to shape the input signal into a square wave. The T3
input is sampled at a frequency of
1
3
×
f
osc
by the sample
clock which synchronizes the internal T3 clock and the
read operation of Derivative Register 24. The rising edge
of the input increments the ripple counter by 1.
The contents of T3 may be read using the instruction
MOV A, D24 (where D24 is Derivative Register 24). As
soon as the data is read, the counter is reset to zero. A
counter overflow or Power-on-reset also resets the
counter contents to zero.
If the rising and falling edges of the input pulse are less
than 30 ns then the minimum pulse width that the T3 input
will recognise is 3/f
osc
+ 100 ns. If the system clock is
10 MHz then the minimum pulse width is 400 ns. In some
display modes, the active pulse width of the Hsync signal
can be less than 400 ns. In this situation, extra hardware
circuitry may be necessary.
handbook, halfpage
tH
tL
0.9 VDD
0.1 VDD
0.1 VDD
0.9 VDD
tr
tr
tf
MGC719
tf
Fig.32 T3 input waveform.
Fig.33 Block diagram of the 8-bit counter (T3).
handbook, full pagewidth
MGC717
T3
Power-on-reset
sample clock
READ D24H
EMU
8-BIT COUNTER
RESET
Q0 to Q7
CK
Data bus
SYNCHRONISATION
CIRCUIT
T3 COUNTER
CONTROL CIRCUIT
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| PCE84C886 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Microcontroller for monitor OSD and auto-sync applications |
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