參數(shù)資料
型號: PCE84C882
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Microcontroller for monitor OSD and auto-sync applications(監(jiān)視器屏幕顯示和自動同步應(yīng)用的微控制器)
中文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, PLASTIC, SDIP-42
文件頁數(shù): 24/60頁
文件大?。?/td> 409K
代理商: PCE84C882
1996 Jan 08
24
Philips Semiconductors
Preliminary specification
Microcontroller for monitor OSD
and auto-sync applications
PCE84C882
10.2
Default values of OSD after Power-on-reset
Frequency of OSD clock: undefined, must be
programmed
Background/Shadowing mode: No background mode
Background/Shadowing colour: blue
Character size: 1H/1V
OSD disabled
Full 64 display RAM displayed (End of display bit = 0)
VOW1E and VOW0E disabled
Horizontal starting position: 5th dot
Vertical starting position: 256th scan-line
Polarity of HSYNCN: active LOW
Polarity of VSYNCN: active LOW
Output polarities of FB, VOW0 to VOW2: active HIGH
Blinking ratio: 3 : 1
Blinking frequency:
1
128
×
f
Vsync
Frame background colour: blue.
After a Power-on-reset, the OSD can be set-up as required
by selecting the Space Code as the first character
(address 0) and the Carriage Return Code as the next
character (address 1). This procedure allows the user to
select the initial background colour; character size and
inter-line spacing.
10.3
Loading character data into display RAM
Three Derivative Registers are used to address and load
data into the display RAM. These registers are described
below.
10.3.1
DCR A
DDRESS
R
EGISTER
(DCRAR)
This is Derivative Register 30 and holds the address of the
location in display RAM to which the data held in registers
DCRTR and DCRCR will be written to. 1 of 64 locations
can be addressed. Bits 7 and 6 are reserved. The contents
of this register are automatically incremented after each
write operation to a RAM address, and become zero on
overflow.
Table 13
DCR Address Register (DCRAR)
7
6
5
4
3
2
1
0
A5
A4
A3
A2
A1
A0
10.3.2
DCR A
TTRIBUTE
R
EGISTER
(DCRTR)
This is Derivative Register 31 and holds the character font
attribute data. The data will be loaded into bits <3-0> of the
location in RAM pointed to by the contents of DCRAR.
Bits 7 to 4 are reserved.
Table 14
DCR Attribute Register (DCRTR)
10.3.3
DCR C
HARACTER
R
EGISTER
(DCRCR)
This is Derivative Register 32 and holds the character data
that will be loaded into bits <9-4> of the location in RAM
addressed by the contents of DCRAR. Bits 7 and 6 are
reserved.
Table 15
DCR Character Register (DCRCR)
10.4
Writing character data into display RAM
The procedure for writing character data into the display
RAM is as follows:
1.
Select the start address in display RAM. The start
address is stored in DCRAR and can take any value
between 0 and 63.
2.
Load the character attributes into DCRTR. If the
attributes of a series of displayed characters are the
same, only DCRCR needs to be updated.
3.
Load the character data into DCRCR. The character
data will specify either a Character Font Code, the
Carriage Return Code or the Space Code. This
operation loads the selected RAM location with the
data held in registers DCRTR and DCRCR. The
address held in DCRAR is then incremented by ‘1’
pointing to the next RAM location in anticipation of the
next operation.
After a master reset the contents of DCRAR, DCRTR and
DCRCR are zero.
7
6
5
4
3
2
1
0
T3
T2
T1
T0
7
6
5
4
3
2
1
0
C5
C4
C3
C2
C1
C0
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