參數(shù)資料
型號(hào)： PAC7111
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 52/56頁(yè)
文件大?。?/td> 471K
代理商： PAC7111
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Mechanical Information
Freescale Semiconductor
52
v1.0
14-Sep-04
(continued)
Section 3, “Electrical Characteristics”
Section 3.2, “Absolute Maximum Ratings”
—
A1a
renamed to V
DD
X
—
A4
“rating” changed to Analog (from ATD)
—
A9
minimum changed to –0.3
—
A12
maximum value removed, footnote reference added
—
Table 8
,
Table 9
footnotes added regarding V
DD
5/V
SS
5
Section 3.4, “Operating Conditions”
—
C1
renamed to V
DD
X
—
C4
added (
C5
to
C11b
renumbered)
—
C8
maximum changed from 40 MHz to 50 MHz
Section 3.5, “Input/Output Characteristics”
—
Table 8
spec
D4
updated (from TBD)
—
Table 9
spec
E4
changed to 1
μ
A to match
D4
Section 3.6, “Power Dissipation and Thermal Characteristics”
— Reworked
Equation 1
through
Equation 4
and supporting text
—
Section 3.6.1
and
Table 10
name changed from “Power Dissipation...”
Section 3.7, “Power Supply”
— Added MAC71
x
1 designation and footnotes to
Table 15
/
Table 16
—
Table 15
designated for 40 MHz, and
– Numerous TBD entries replaced with values
– Run Supply Current collapsed from fifteen spec items to one
– Removed separate Core/Regulator/Pins specs for Run/Pseudo Stop/Stop modes
–
F1
and
F3
descriptions changed
–
F1
,
F2
,
F3
and
F4
values updated
—
Table 16
added for 50 MHz specifications
—
Table 17
, deleted I
REG
spec (Regulator Current in Reduced Power, Shutdown Modes)
—
Table 18
, V
DD
2.5 load capacitance typical changed, with clarification footnote
Section 3.8, “Clock and Reset Generator”
—
Table 19
updates
– Changed specs
J1b
and
J6
maximum from 40 MHz to 50 MHz
– Reversed polarity of XCLKS reference in footnote (
3
)
–
J1b
maximum changed to 40 MHz
– V
DCBIAS
removed
– Added footnote to define t
fsys
as 1
÷
f
SYS
for use elsewhere in the document
— Updated
Section 3.8.2, “PLL Filter Characteristics”
—
Table 20
updates
– Changed spec
K3
maximum from 40 MHz to 50 MHz
– Added footnote to define t
fsys
as 1
÷
f
SYS
for use elsewhere in the document
—
Table 23
updates
– Removed V
PORR
and V
PORA
, as they duplicated
H6
– Removed t
WRS
Section 3.9, “External Bus Timing”
—
Table 24
updates
–
M1
minimum changed from 25 ns to 20 ns (
Figure 6
also updated)
– Reworded footnote (
1
)
– Added footnote (
2
) to define t
CYC
as 1
÷
CLKOUT
—
Table 25
updates
– Added footnote (
1
)
– Consolidated previous NOTES into footnote (
2
), (
Figure 7
,
Figure 8
also updated)
4
4
5
5
7
,
8
6
6
6
7
8
9
10
12
12
13
14
15
16
18
19
20
21
Revision History (continued)
Version No.
Release Date
Description of Changes
Page
Numbers
相關(guān)PDF資料
PDF描述
PAC7112 Microcontroller Family Hardware Specifications
PAC7116 Microcontroller Family Hardware Specifications
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PAC7112 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
PAC7116 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
PAC7121 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
PAC7122 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
PAC7126 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller Family Hardware Specifications
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