參數(shù)資料
型號(hào)： PAC7111
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 26/56頁(yè)
文件大小： 471K
代理商： PAC7111
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
26
3.10.2 ATD Accuracy
Table 29
and
Table 30
specify the ATD conversion performance excluding any errors due to current
injection, input capacitance and source resistance.
For the following definitions, see
Figure 9
.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps:
Eqn. 17
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
Eqn. 18
Table 29. ATD Conversion Performance in 5.0 V Range
Conditions shown in
Table 7
except as noted here:
f
ATDCLK
= 2.0 MHz, 4.5 V
≤
V
DD
A
≤
5.5 V
Num C
Rating
Symbol
Min
Typ
5
1
—
±
1.5
±
2.0
20
1
—
±
0.5
±
1.0
Max
Unit
R1
R2
R3
R4
R5
R6
R7
R8
P 10-bit Resolution
P 10-bit Differential Nonlinearity
P 10-bit Integral Nonlinearity
P 10-bit Absolute Error
2
P 8-bit Resolution
P 8-bit Differential Nonlinearity
P 8-bit Integral Nonlinearity
P 8-bit Absolute Error
2
LSB
DNL
INL
AE
LSB
DNL
INL
AE
—
–1
–2.5
–3
—
–0.5
–1.0
–1.5
NOTES:
1. Assumes V
REF
= V
RH
– V
RL
= 5.12 V, other V
REF
conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently count for any A/D converter.
—
1
2.5
3
—
0.5
1.0
1.5
mV
Counts
Counts
Counts
mV
Counts
Counts
Counts
Table 30. ATD Conversion Performance in 3.3 V Range
Conditions shown in
Table 7
except as noted here:
f
ATDCLK
= 2.0 MHz, 3.15 V
≤
V
DD
A
≤
3.6 V
Num C
Rating
Symbol
Min
Typ
3.25
1
—
±
1.5
±
2.0
13
1
—
±
1.0
±
1.0
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
P 10-bit Resolution
P 10-bit Differential Nonlinearity
P 10-bit Integral Nonlinearity
P 10-bit Absolute Error
2
P 8-bit Resolution
P 8-bit Differential Nonlinearity
P 8-bit Integral Nonlinearity
P 8-bit Absolute Error
2
LSB
DNL
INL
AE
LSB
DNL
INL
AE
—
–1.5
–3.5
–5
—
–0.5
–1.5
–1.5
NOTES:
1. Assumes V
REF
= V
RH
– V
RL
= 3.33 V, other V
REF
conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently count for any A/D converter.
—
1.5
3.5
5
—
0.5
1.5
1.5
mV
Counts
Counts
Counts
mV
Counts
Counts
Counts
DNL i
( )
V
----------------------
V
1
–
–
1 LSB
1
–
=
INL n
DNL i
( )
i
1
=
n
∑
V
1 LSB
0
-------–
n
–
=
=
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