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Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
179
Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem.
Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select
output.
2.4.3.12
Port AD0
This port is associated with the ATD0.
Port AD0 pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.3.13
Port AD1
This port is associated with the ATD1.
Port AD1 pins PAD[31:16] can be used for either general purpose I/O, or with the ATD1 subsystem.
2.4.3.14
Port R
This port is associated with the TIM module.
PortRpinsPR[7:0]canbeusedforeithergeneral-purposeI/O,orwiththechannelsofthestandardTimer.
The TIM channels can be re-routed.
2.4.3.15
Port L
This port is associated with SCI7-4.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI7 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with SCI6 subsystem.
Port L pins PL[3:2] can be used for either general purpose I/O, or with SCI5 subsystem.
Port L pins PL[1:0] can be used for either general purpose I/O, or with SCI4 subsystem.
2.4.3.16
Port F
This port is associated with SCI3, IIC0 and chip selects.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem.
Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects.
2.4.4
Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
fallingedgescanbeindividuallyconfiguredonper-pinbasis.Allbits/pinsinaportsharethesameinterrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.