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Data Sheet Revision 1.1
Page 9
OXCB950
OXFORD SEMICONDUCTOR LTD.
Multi-purpose & External
interrupt pins
26
27
Dir
1
Name
Description
T_I/O
T_I/O
MIO[0]
MIO[1]
Multi-purpose I/O pins.
Can be driven high or low, or be used to invoke
cardbus/PCI interrupts, and powerdown, wakeup requests.
EEPROM pins
28
29
31
O
O
IU
EE_CK
EE_CS
EE_DI
EEPROMclock
EEPROMactive-high Chip Select
EEPROMdata in (to be connected to the EEPROMDO
pin).
When the optional serial EEPROMis connected, this pin
should be pulled up using an external 110k resistor. When
the EEPROMis not used, this external pull-up is not
required (internal pull-up is sufficient).
EEPROMdata out. (to be connected to the EEPROMDI
pin)
30
O
EE_DO
Miscellaneous pins
34
33
ID
ID
TEST0
TEST1
Test Pin 0. Should be held low at all times.
Test Pin 1. Should be held low at all times
Power and ground
2
89, 14, 63
V
VDD3I_CB
Supplies power to the pre-drive area of the dual mode
cardbus/pci IO buffers.
Supplies power to the output drive of the dual mode
cardbus/pci IO buffers.
Supplies power to the core-logic and pre-drive area of the
standard IO buffers.
Suppiles power to the outputdrive of standard IO buffers.
Supplies ground to the pre-drive area of the dual mode
cardbus/pci IO buffers.
Supplies ground to the output drive of the dual mode
cardbus/pci IO buffers.
Supplies gnd to the core-logic and pre-drive area of the
standard IO buffers.
Supplies gnd to the output drive of standard IO buffers.
56, 71, 81, 91, 7, 21
V
VDD3OP_CB
38, 39
V
VDDIP
41,
V
G
VDDO
VSSI_CB
62, 87, 13
55, 64,65,70, 76, 82, 90, 92, 97,
2, 6, 12, 20,
35
G
VSSOP_CB
G
VSSIP
40, 50
G
VSSO
Table: Pin Descriptions
Note 1: Direction key:
I
3.3v Input, TTL compatible
ID
3.3v Input with pull-down, TTL compatible
IU
3.3v Input with pull-up, TTL compatible
O
3.3v Output, TTL compatible
T_O
5.0v tolerant TTL output
T_I
5.0v tolerant TTL input
T_I/O
5.0v tolerant TTL Bi-directional
Note 2: Power & Ground
There are several types of VDD and VSS in this design, providing not only power for the internal (core) and I/O pad area but also
special power lines to the dual mode cardbus/pci I/O buffers. These power rails are not connected internally.
This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation fromthe chip. Further
precaution is taken by segmenting the GND and VDD rails to isolate the PCI and UART pins.
C/P_I
C/P_O
C/P_I/O Cardbus/PCI compatible bi-directional
C/P_OD Cardbus/PCI compatible open drain
G
Ground
V
3.3V power
Cardbus/PCI compatible input
Cardbus/PCI compatible output