- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384806 > OXCB950 (Electronic Theatre Controls, Inc.) Integrated High Performance UART Cardbus / PCI interface PDF資料下載
參數(shù)資料
| 型號： | OXCB950 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance UART Cardbus / PCI interface |
| 中文描述： | 綜合高性能的UART Cardbus / PCI接口 |
| 文件頁數(shù)： | 17/68頁 |
| 文件大?。?/td> | 409K |
| 代理商： | OXCB950 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Data Sheet Revision 1.1
Page 17
OXCB950
OXFORD SEMICONDUCTOR LTD.
Bits
23
Description
Enable Cardbus Status Registers
When set (1), all interrupt sources and power management events are
controlled by the INTR, GWAKE/WKUP fields of the cardbus status
registers.
This bit has meaning only for cardbus applications
EEPROM Clock
. For reads or writes to the external EEPROM, toggle
this bit to generate an EEPROMclock (EE_CK pin).
EEPROM Chip Select
. When 1 the EEPROMchip-select pin EE_CS is
activated (high). When 0 EE_CS is de-active (low).
EEPROM Data Out
. For writes to the EEPROM this output bit feeds the
input-data of the external EEPROM This bit is output on the devices
EE_DO and clocked into the EEPROMby EE_CK.
EEPROM Data In
. For reads fromthe EEPROM this input bit is the
output-data (D0) of the external EEPROMconnected to EE_DI pin.
EEPROMValid
.
A 1 indicates that a valid EEPROMprogramheader is present
Reload configuration from EEPROM
.
Writing a 1 to this bit re-loads the configuration fromEEPROM This bit is
self-clearing after an EEPROMread
Reserved
Reserved
Read/Write
EEPROM
W
Reset
0
PCI
R/W
24
-
RW
0
25
-
RW
0
26
-
RW
0
27
-
R
1
28
-
R
X
29
-
RW
0
30
31
-
-
R
R
0
0
6.4.2
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0]’ as follows.
Bits
Description
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
4
MIO0 Power Management Event Enable
.
A value of ‘1’ enables the MIO0 pin to set the PME_Status bit in the PCI
PMCSR register, and hence assert the PME#
(pci
) or CSYSCHG
(
cardbus
) pin if this option has been enabled.
A value of ‘0’ prevents MIO0 fromsetting the PCI PME_Status bit.
5
MIO1 Power Management Event Enable
.
A value of ‘1’ enables the MIO1 pin to set the PME_Status bit in the PCI
PMCSR register, and hence assert the PME#
(pci
) or CSYSCHG
(
cardbus
) pin if this option has been enabled.
A value of ‘0’ prevents MIO1 fromsetting the PCI PME_Status bit.
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
Read/Write
EEPROM
W
Reset
00
PCI
RW
W
RW
00
W
RW
0
W
RW
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OXFW900 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW900-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OZ6812 | ACPI CardBus Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OXCB950-TQAG | 功能描述:外圍驅(qū)動器與原件 - PCI 32 bit PC Card bridge to serial prt RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OXCB950-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance UART Cardbus / 3.3v PCI interface |
| OXCF950 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950_06 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950B | 制造商:PLX 制造商全稱:PLX 功能描述:16-bit PC card/CF+ bridge to serial port |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。