- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384806 > OXCB950 (Electronic Theatre Controls, Inc.) Integrated High Performance UART Cardbus / PCI interface PDF資料下載
參數(shù)資料
| 型號： | OXCB950 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance UART Cardbus / PCI interface |
| 中文描述： | 綜合高性能的UART Cardbus / PCI接口 |
| 文件頁數(shù)： | 19/68頁 |
| 文件大?。?/td> | 409K |
| 代理商： | OXCB950 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
6.4.4
This register controls the assertion of interrupts and power management events, as well as returning the internal status of all
interrupt sources and power management events.
Bits
Description
1:0
Reserved
2
MIO0 Internal State.
This bit reflects the state of the internal MIO[0] signal. The internal MIO[0]
signal reflects the non-inverted or inverted state of MIO0 pin.
2
3
MIO1 Internal State
This bit reflects the state of the internal MIO[1] signal. The internal MIO[1]
reflects the non-inverted or inverted state of MIO1 pin.
2
17-4
Reserved
18
MIO0 Interrupt Enable
When set (1) allows the pin MIO0 to assert an interrupt on the device’s INTA#
(CINT#) pin. The state of the MIO0 signal that causes an interrupt is
dependant upon the polarity set by the register fields MIC(1:0)
19
MIO1 Interrupt Enable
When set (1) allows the pin MIO1 to assert an interrupt on the device’s INTA#
(CINT#) pin. The state of the MIO1 signal that causes an interrupt is
dependant upon the polarity set by the register fields MIC(3:2)
20
Power-down Internal Interrupt Status.
This is a sticky bit. When set, it indicates that a power-down request has been
recognised (validated), which would normally have asserted a powerdown
interrupt on the INTA#(CINT#) pin if GIS bit 21 was set.
Reading this bit clears the Internal Powerdown Interrupt Status.
21
Power-down interrupt enable
.
When set to ‘1’, a powerdown request is allowed to generate an interrupt on
the INTA#/ (CINT# ) pin.
22
UART interrupt status
. 1
This bit reflects the interrupt status of the internal UART.
23
UART Interrupt Enable
.
When set (1) allows the UART to assert an interrupt on the device’s INTA#
(CINT# ) pin
3
24
UART Power Management Event Enable
A value of ‘1’ enables the UART ‘wakeup events to set the PME_Status bit in
the PCI PMCSR register, and hence assert the PME#
(pci
) or CSYSCHG
(
cardbus
) pin if this option has been enabled.
A value of ‘0’ prevents any wakeup events fromthe UART fromsetting the
PCI PME_Status bit.
25
UART Powerdown Filter Control
A ‘1’ enables the UART to invoke a powerdown request via the power down
filter (if the filter is enabled).
31:24
Reserved
Data Sheet Revision 1.1
Page 19
OXCB950
OXFORD SEMICONDUCTOR LTD.
Global Interrupt Status and Control Register ‘GIS’ (Offset 0x0C)
Read/Write
EEPROM
-
-
Reset
PCI
R
R
0x0h
X
-
R
X
-
W
R
RW
0
1
W
RW
1
-
R
X
W
RW
0
-
R
0
W
R/W
1
W
R/W
0
W
R/W
0
-
R
00h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OXFW900 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW900-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OZ6812 | ACPI CardBus Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OXCB950-TQAG | 功能描述:外圍驅(qū)動器與原件 - PCI 32 bit PC Card bridge to serial prt RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OXCB950-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance UART Cardbus / 3.3v PCI interface |
| OXCF950 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950_06 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950B | 制造商:PLX 制造商全稱:PLX 功能描述:16-bit PC card/CF+ bridge to serial port |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。