參數(shù)資料
型號: OX16CF950
廠商: Electronic Theatre Controls, Inc.
英文描述: LOW COST ASYNCHRONOUS 16 BIT CARD
中文描述: 低成本異步16位卡
文件頁數(shù): 17/60頁
文件大?。?/td> 753K
代理商: OX16CF950
Page 17
OXCF950 DATA SHEET V1.1
OXFORD SEMICONDUCTOR LTD.
If a PCMCIA/CF card is using the I/O interface and this field is reset to zero (0),
the function shall not assert STSCHG#.
If a PCMCIA/CF card is not using the I/O interface or the function’s Pin
Replacement register is not present, this field is undefined and should be
ignored.
The host sets this field to one (1) when it can provide I/O cycles only with an 8-bit
D[7..0] data path. The card is guaranteed that accesses to the 16-bit registers will
occur as two byte accesses rather than as a single 16-bit access.
Reserved. Must be zero (0).
This bit is set to one (1) to enable audio information on SPKR# when the card is
configured.
When the host sets this field to one (1), the function shall enter a power-down
state, if such a state exists.
If a PCMCIA/CF card function does not have a power-down state, the function
shall ignore this field.
Interrupt Request / Acknowledge – This field reports whether the function is
requesting interrupt servicing and may be used to acknowledge the host system
is ready to process another interrupt request from the PCMCIA/CF card.
The function shall set this field to one (1) when it is requesting interrupt service.
The function shall set this field to zero (0) when it is not requesting interrupt
service.
Writes to this field are ignored when the IntrAck field of all Configuration and
Status Registers on the PCMCIA/CF card are reset to zero (0).
Single function cards ignore this field on writes and always return zero (0).
IOIs8
R/W
RFU
Audio
2
-
R/W
PwdDwn
3
R/W
Intr
R
IntrAck
R/W
Table 15: Configuration Status Register
Note 1
The STSCHG# signal is optional and is not supported on the OXCF950, to reduce the complexity of the device.
Note 2
Audio is not supported on the device.
Note 3
The OXCF950 does not support a specific power down mode, since it is a low power device that features a number of sleep
modes (see Section 7 for further details).
5.5.3
Pin Replacement Register ‘PRR’ (Offset 0xFC)
The Pin Replacement Register is implemented to provide information about READY, WP or the BVD[2..1] status when
implementing the I/O interface.
D7
D6
D5
D4
CBVD1
CBVD2
CREADY
CWProt
Field
Description
CBVD1
This bit is set (1) when the corresponding bit, RBVD1, changes state. This bit may also be
written by the host.
CBVD2
This bit is set (1) when the corresponding bit, RBVD2, changes state. This bit may also be
D3
D2
D1
D0
RBVD1
RBVD2
RREADY
RWProt
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