參數(shù)資料
型號： OX16C954-PCC60-B
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述： UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁數(shù)： 10/54頁
文件大?。?/td> 529K
代理商： OX16C954-PCC60-B
Data Sheet Revision 1.0
Page 10
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
4 P
IN
D
ESCRIPTIONS
Please refer to Section 3 for actual Signal Name to Pin Number assignments, for the selected package.
TQFP
PLCC
Dir
1
Name
Description
Clock
50
35
I
XTLI
Crystal oscillator input or external clock pin, for the UART channels.
Crystal oscillator frequency maximum60MHz
51
36
O
XTLO
Crystal oscillator output.
Not used when an alternative TTL level clock is applied to XTLI and can
be left unconnected
45
30
I
CLKSEL
This pin is provided to select an internal clock prescaler on power up. In
16C554 devices this pin is a VDD. When CLKSEL pin is high the internal
prescaler is bypassed (a 1.8432MHz clock is assumed). Connect this pin
to GND to enable the internal clock prescaler. The complement of this pin
is loaded in bit 7 of the MCR register after a hardware reset.
This pin can also be used as an alternative external clock pin under
software control (replacing XTLI and thus reducing noise/power due to
XTLO) for embedded applications.
Processor Interface Pins in Intel Mode (I/M#= ‘1’)
53
37
I
hysteresis to provide noise immunity. This pin must be tied inactive when
not in use.
73
68
33
28
16
I
CS[0]#
CS0# - Chip select for Uart 0
46 to 48
32 to 34
I
A[2:0]
Address lines to select the Uart (channel) registers.
15 to 11
9 to 7
68 to 66
31
18
I
IOW#
Active-low write strobe in Intel bus mode.
70
52
I
IOR#
Active-low read strobe in Intel bus mode.
Processor Interface Pins in Motorola Mode (I/M#= ‘0’)
53
37
I
RESET#
Active-low Hardware Reset. The configuration of OX16C954 after a
hardware reset is described in section 7.1. This pin exhibits a small
hysteresis to provide noise immunity. This pin must be tied inactive when
not in use.
28
16
I
DS#
Active-low Data-Strobe.
(In Motorola bus mode, individual registers are accessed using DS#
R/W#and A[4:0])
70
73
54
I
VDD or GND.
68
33
20
I
A3
RESET
Active-high Hardware Reset. The configuration of OX16C954 after a
hardware reset is described in section 7.1. This pin exhibits a small
54
50
20
I
I
I
CS[3]#
CS[2]#
CS[1]#
Active-low Chip-Selects for each Uart channel, in Intel bus mode.
CS3# - Chip select for Uart 3
CS2# - Chip select for Uart 2
CS1# - Chip select for Uart 1
5 to 1
I/O
DB[7:0]
Eight-bit 3-state data bus.
52
I
UNUSED
In Motorola bus mode these pins are unused and must be connected to
50
I
A4
The A[4:3] combination selects individual channels as follows:
00 = UART 0 selected
01 = UART 1 selected
10 = UART 2 selected
11 = UART 3 selected
Address lines to select the UART (channel) registers.
46 to 48
32 to 34
I
A[2:0]
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