參數(shù)資料
型號： ORT82G5-3F680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 96/119頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
78
Input Eye-Mask Characterization
Figure 39. provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specied below
for two different eye-mask heights. It provides guidance on a number of input parameters, including signal ampli-
tude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental character-
istics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eye-
opening limitations of the line receiver, can provide a good indication of a link’s ability to transfer data error-free.
The Clock and Data Recovery (CDR) portion of the ORT42G5 and ORT82G5 SERDES receiver has the ability to
lter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specica-
tions of Table 37 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition.
When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is signicantly better. For
this case error-free data detection can occur even with a completely closed eye-mask.
Figure 39. Receive Data Eye-Diagram Template (Differential)
Table 37. Receiver Eye-Mask Specications1
Parameter
Conditions
Value
Unit
Input Data
Eye Opening Width (H)@ 3.125Gbps
V=175 mV diff
1
0.55
UIP-P
Eye Opening Width (T)@ 3.125Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 3.125Gbps
V=600 mV diff
1
0.35
UIP-P
Eye Opening Width (T)@ 3.125Gbps
V=600 mV diff
1
0.10
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=175 mV diff
1
0.42
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=600 mV diff
1
0.33
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=600 mV diff
1
0.10
UIP-P
1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter
of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V supply.
H
V
1.2V
UI
T
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