- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1958 > ORT82G5-3F680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF資料下載
參數(shù)資料
| 型號： | ORT82G5-3F680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 95/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁當前第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
77
High Speed Data Receiver
Table 35 species receiver parameters measured on devices with worst case process parameters and over the full
range of operation conditions.
Table 35. External Data Input Specications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g XAUI, FC, Infiniband etc.). Sinusoidal
jitter is considered to be a worst case jitter type. Table 36 shows receiver specifications with 10 MHz sinusoidal jit-
ter injection. XAUI specic jitter tolerance measurements were measured in a separate experiment detailed in tech-
nical note TN1032, SERDES Test Chip Jitter, and are not reected in these results.
Table 36. Receiver Sinusoidal Jitter Tolerance Specications
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Data
Stream of Nontransitions
8b/10b encode/decode off
—
72
Bits
Sensitivity (differential), worst-case
1
3.125 Gbps
80
—
mVp-p
Input Levels
2
—
VSS - 0.3
—
VDD_ANA + 0.3
V
Internal Buffer Resistance (Each input to VDDIB)
—
40
50
60
Ω
PLL Lock Time
3
—
Note 2
—
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V sup-
ply.
2. Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2
3. The ORT42G5 and ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing rst
bit, then byte (character), then channel (32-bit word), and nally optional multi-channel alignment as described in TN1025. The PLL Lock
Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to
lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back
to the serial data stream to again attempt synchronization.
Parameter
Conditions
Max.
Unit
Input Data
Jitter Tolerance @3.125Gbps, Typical
600 mV diff eye
1
0.75
UIP-P
Jitter Tolerance @3.125Gbps, Worst case
600 mV diff eye
1
0.65
UIP-P
Jitter Tolerance @2.5Gbps,Typical
600 mV diff eye
1
0.79
UIP-P
Jitter Tolerance @2.5Gbps, Worst case
600 mV diff eye
1
0.67
UIP-P
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V
to 1.575V supply. Jitter measured with a Wavecrest SIA-3000.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT8850L-1BMN680I | IC TRANCEIVERS FPSC 680FPGAM |
| ORT8850L-3BM680C | IC FPSC TRANSCEIVER 8CH 680-BGA |
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。