參數(shù)資料
型號： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 64/110頁
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
57
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
*For XAUISTAT_By[0:1] (address 0x30904), the denitions of these bits are:
00—No synchronization.
10—Synchronization done.
01,11—Not used.
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
Status Register B
30904
B16
XAUISTAT_BA[0:1]*
Status of XAUI link state
machine for bank B, channel A
XAUISTAT_BB[0:1]*
Status of XAUI link state
machine for bank B, channel B
XAUISTAT_BC[0:1]*
Status of XAUI link state
machine for bank B, channel C
XAUISTAT_BD[0:1]*
Status of XAUI link state
machine for bank B, channel D
00
30905
B17
DEMUXWAS_
BA
Status of
deMUX word
alignment for
bank B, chan-
nel A
DEMUXWAS_
BB
Status of
deMUX word
alignment for
bank B, chan-
nel B
DEMUXWAS_
BC
Status of
deMUX word
alignment for
bank B, chan-
nel C
DEMUXWAS_
BD
Status of
deMUX word
alignment for
bank B, chan-
nel D
CH248_SYNC
_BA
Alignment
completed for
BA
CH248_SYNC
_BB
Alignment
completed for
BB
CH248_SYNC
_BC
Alignment
completed for
BC
CH248_SYNC
_BD
Alignment
completed for
BD
00
30906
B18
Reserved for future use
30907
B19
Reserved for future use
30914
B20
SYNC2_B1_O
VFL
Alignment
FIFO overow
for BA and BB
SYNC2_B2_O
VFL
Alignment
FIFO overow
for BD and BC
SYNC4_B_O
VFL
Alignment
FIFO overow
for B[A:D]
SYNC2_B1_O
OS
Alignment out
of sync for BB
and BA
SYNC2_B2_O
OS
Alignment out
of sync for BC
and BD
SYNC4_B_O
OS
Alignment out
of sync for
B[A:D]
Reserved for Future Use
00
30915
B21
Reserved for future use
30916
B22
Reserved for future use
30917
B23
Reserved for future use
30924
B24
Reserved for future use
30925
B25
Reserved for future use
30926
B26
Reserved for future use
30927
B27
Reserved for future use
30934
B28
Reserved for future use
30935
B29
Reserved for future use
30936
B30
Reserved for future use
30937
B31
Reserved for future use
相關PDF資料
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ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
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相關代理商/技術參數(shù)
參數(shù)描述
ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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