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| 型號： | ORCAORT8850 |
| 英文描述： | Single 2.3V PNP in OP, I temp, -40C to +85C, 8-MSOP, T/R |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 62/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT8850 |
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ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
62
L Lucent Technologies Inc.
Pin Information
(continued)
Table 39. FPGA Common-Function Pin Description
(continued)
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Symbol
I/O
Description
Special-Purpose Pins
(continued)
MPI_IRQ
MPI_BI
O
O
I/O
O
MPI active-low interrupt request output.
PowerPC mode MPI burst inhibit output.
If the MPI is not in use, this is a user-programmable I/O.
In PowerPCmode MPI operation, this is the active-high transfer acknowledge (TA)
output. For i960 MPI operation, it is the active-low ready/record (RDYRCV) output.
If the MPI is not in use, this is a user-programmable I/O.
In PowerPCmode MPI operation, this is the active-low write/active-high read control
signals. For i960operation, it is the active-high write/active-low read control signal.
If the MPI is not in use, this is a user-programmable I/O.
This is the clock used for the synchronous MPI interface. For PowerPC it is the CLK-
OUT signal. For i960, it is the system clock that is chosen for the i960 external bus
interface.
If the MPI is not in use, this is a user-programmable I/O.
For PowerPCoperation, these are the PowerPCaddress inputs. The address bit
mapping (in PowerPCFPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/
A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs
are not used in i960 MPI mode.
If the MPI is not in use, this is a user-programmable I/O.
For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that
are used as address bits A[1:0] in i960byte-wide operation.
During peripheral and slave parallel configuration modes, D[7:0] receive configura-
tion data, and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode
and the address/data pins for i960 microprocessor mode.
After configuration, the pins are user-programmable I/O pins.*
During slave serial or master serial configuration modes, DIN accepts serial configu-
ration data synchronous with CCLK. During parallel configuration modes, DIN is the
D0 input. During configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin.*
During configuration, DOUT is the serial data output that can drive the DIN of daisy-
chained slave LCA devices. Data out on DOUT changes on the falling edge of
CCLK.
After configuration, DOUT is a user-programmable I/O pin.*
MPI_ACK
MPI_RW
I
I/O
I
MPI_CLK
I/O
I
A[4:0]
I/O
I
A[1:0]/MPI_BE[1:0]
D[7:0]
I
I/O
I
DIN
I/O
O
DOUT
I/O
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