Data Sheet
June 1999
ORCA Series 2 FPGAs
96
Lucent Technologies Inc.
E19
D20
E18
D19
C20
E17
D18
C19
B20
C18
B19
A20
A19
B18
B17
C17
D16
A18
A17
C16
B16
A16
C15
D14
B15
A15
C14
B14
A14
C13
B13
A13
D12
C12
B12
A12
B11
C11
A11
A10
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
—
—
—
—
RD_CFGN
—
PT12D
PT12C
PT12B
PT12A
—
PT11D
PT11C
PT11B
PT11A
—
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
—
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT13D
PT13C
PT13B
PT13A
PT12D
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PR4B
PR4D
PR3A
PR2A
PR2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
PT16D
PT16C
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PR5B
PR5D
PR4A
PR3A
PR3B
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT20D
PT20C
PT20A
PT19D
PT19A
PT18A
PT17D
PT17C
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
I/O
I/O
I/O-V
DD
5
I/O-
WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFGN
I/O
I/O
I/O
I/O
I/O-
RDY/RCLK
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O-V
DD
5
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
I/O
I/O
I/O
I/O-D3
Pin Information
(continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout
(continued)
Pin
2C/2T06A Pad
2C/2T08A Pad
2C/2T10A Pad
2C/2T12A Pad
2C/2T15A/B Pad
Function
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-V
DD
5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to V
DD
5 for the OR2TxxA series.
The pins labeled V
SS
-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.