![](http://datasheet.mmic.net.cn/370000/OR2T04A-2PS84_datasheet_16726875/OR2T04A-2PS84_93.png)
Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
93
P3
R2
T1
P4
R3
T2
U1
T3
U2
V1
T4
U3
V2
W1
V3
W2
Y1
Y2
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
U7
W6
Y6
V7
W7
Y7
V8
W8
Y8
U9
V9
W9
Y9
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
—
PL12D
PL12C
PL12B
—
—
—
PL12A
CCLK
PB1A
—
PB1B
PB1C
PB1D
—
—
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PL12D
PL12C
PL12B
PL13D
PL13B
PL13A
PL14D
PL14C
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3B
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PL13D
PL13B
PL14D
PL14B
PL14A
PL15D
PL15B
PL16D
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3D
PB4D
PB5A
PB5B
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PL14D
PL14B
PL15D
PL15B
PL15A
PL16D
PL16B
PL17D
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20A
CCLK
PB1A
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
I/O-A12
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O-A14
I/O-V
DD
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
I/O
I/O
I/O-V
DD
5
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Information
(continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout
(continued)
Pin
2C/2T06A Pad
2C/2T08A Pad
2C/2T10A Pad
2C/2T12A Pad
2C/2T15A/B Pad
Function
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-V
DD
5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to V
DD
5 for the OR2TxxA series.
The pins labeled V
SS
-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.