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參數(shù)資料
型號(hào)： OPA659IDBVR
廠商： Texas Instruments
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP JFET 650MHZ SGL SOT23-5
標(biāo)準(zhǔn)包裝： 3,000
放大器類型： J-FET
電路數(shù)： 1
轉(zhuǎn)換速率： 2550 V/µs
增益帶寬積： 350MHz
-3db帶寬： 650MHz
電流 - 輸入偏壓： 10pA
電壓 - 輸入偏移： 1000µV
電流 - 電源： 32mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： ±3.5 V ~ 6.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SC-74A，SOT-753
供應(yīng)商設(shè)備封裝： SOT-23-5
包裝： 帶卷 (TR)
Board Layout
www.ti.com ............................................................................................................................................ SBOS342B – DECEMBER 2008 – REVISED AUGUST 2009
device
performance.
Good
axial
metal
film
or
surface-mount resistors have approximately 0.2pF in
Achieving
optimum
performance
with
a
shunt with the resistor. For resistor values greater
high-frequency
amplifier
such
as
the
OPA659
than 1.5k
, this parasitic capacitance can add a pole
requires careful attention to PCB layout parasitics and
and/or zero below 500MHz that can affect circuit
external component types. Recommendations that
operation. Keep resistor values as low as possible,
can
optimize
device
performance
include
the
consistent with load driving considerations. It is
following.
recommended to keep RF || RG less than 250. This
low value ensures that the resistor noise terms
a) Minimize parasitic capacitance to any ac ground
remain low, and minimizes the effects of the parasitic
for all of the signal input/output (I/O) pins. Parasitic
capacitance.
Transimpedance
applications
(for
capacitance on the output and inverting input pins
example, see Figure 37) can use the feedback
can cause instability: on the noninverting input, it can
resistor required by the application as long as the
react
with
the
source
impedance
to
cause
feedback
compensation
capacitor
is
set
given
unintentional
band-limiting.
To
reduce
unwanted
consideration to all parasitic capacitance terms on the
capacitance, a window around the signal I/O pins
inverting node.
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
d) Connections to other wideband devices on the
power planes should be unbroken elsewhere on the
board may be made with short direct traces or
board.
through
onboard
transmission
lines.
For
short
connections, consider the trace and the input to the
b) Minimize the distance (less than 0.25in, or
next device as a lumped capacitive load. Relatively
6,35mm)
from
the
power-supply
pins
to
the
wide traces (50mils to 100mils, or 1,27cm to 2,54cm)
high-frequency, 0.1
F decoupling capacitors. At the
should be used. Estimate the total capacitive load
device pins, the ground and power plane layout
and set RISO from the plot of Recommended RISO vs
should not be in close proximity to the signal I/O pins.
Capacitive Load (Figure 24). Low parasitic capacitive
Use a single point ground, located away from the
loads (less than 5pF) may not need an RISO because
input pins, for the positive and negative supply
the OPA659 is nominally compensated to operate
high-frequency, 0.1
F decoupling capacitors. Avoid
with a 2pF parasitic load.
narrow
power
and
ground
traces
to
minimize
inductance between the pins and the decoupling
Higher parasitic capacitive loads without an RISO are
capacitors. The power-supply connections should
allowed as the signal gain increases (increasing the
always be decoupled with these capacitors. Larger
unloaded phase margin). If a long trace is required,
(2.2
F to 10F) decoupling capacitors, effective at
and
the
6dB
signal
loss
intrinsic
to
a
lower frequencies, should also be used on the supply
doubly-terminated transmission line is acceptable,
pins.
These
larger
capacitors
may
be
placed
implement a matched impedance transmission line
somewhat farther from the device and may be shared
using microstrip or stripline techniques (consult an
among several devices in the same area of the PCB.
ECL design handbook for microstrip and stripline
layout techniques). A 50
environment is normally
c) Careful selection and placement of external
not
necessary
onboard,
and
in
fact
a
higher
components
preserves
the
high-frequency
impedance environment improves distortion as shown
performance of the OPA659. Resistors should be a
in
the
distortion
versus
load
plots.
With
a
very low reactance type. Surface-mount resistors
characteristic board trace impedance defined based
work best and allow a tighter overall layout. Metal film
on board material and trace dimensions, a matching
and carbon composition, axially-leaded resistors can
series resistor into the trace from the output of the
also
provide
good
high-frequency
performance.
OPA659 is used as well as a terminating shunt
Again, keep the leads and PCB trace length as short
resistor at the input of the destination device.
as possible. Never use wirewound-type resistors in a
Remember also that the terminating impedance is the
high-frequency application. The inverting input pin is
parallel combination of the shunt resistor and the
the
most
sensitive
to
parasitic
capacitance;
input impedance of the destination device: this total
consequently, always position the feedback resistor
effective impedance should be set to match the trace
as close to the negative input as possible. The output
impedance.
If
the
6dB
attenuation
of
a
is also sensitive to parasitic capacitance; therefore,
doubly-terminated transmission line is unacceptable,
position a series output resistor (in this case, RISO) as
a long trace can be series-terminated at the source
close to the output pin as possible.
end only. Treat the trace as a capacitive load in this
Other network components, such as noninverting
case, and set the series resistor value as shown in
input termination resistors, should also be placed
the plot of RISO vs Capacitive Load (Figure 24). This
close to the package. Even with a low parasitic
configuration does not preserve signal integrity as
capacitance, excessively high resistor values can
create significant time constants that can degrade
Copyright 2008–2009, Texas Instruments Incorporated
17
Product Folder Link(s): OPA659
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