SBOS342B – DECEMBER 2008 – REVISED" />
參數(shù)資料
型號: OPA659IDBVR
廠商: Texas Instruments
文件頁數(shù): 10/32頁
文件大?。?/td> 0K
描述: IC OPAMP JFET 650MHZ SGL SOT23-5
標(biāo)準(zhǔn)包裝: 3,000
放大器類型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 2550 V/µs
增益帶寬積: 350MHz
-3db帶寬: 650MHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 1000µV
電流 - 電源: 32mA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): ±3.5 V ~ 6.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 帶卷 (TR)
Input and ESD Protection
External
Pin
Internal
Circuitry
-
V
CC
+
V
CC
PowerPAD Information
SBOS342B – DECEMBER 2008 – REVISED AUGUST 2009 ............................................................................................................................................ www.ti.com
well
as
a
doubly-terminated
line.
If
the
input
shown in the EVM layer views (see Figure 41). For
impedance of the destination device is low, there will
more general data and detailed information about the
be some signal attenuation as a result of the voltage
PowerPAD
package,
refer
to
the
PowerPAD
divider
formed
by
the
series
output
into
the
Thermally
Enhanced
Package
application
note
terminating impedance.
e) Socketing a high-speed part such as the
OPA659 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the
The OPA659 is built using a very high-speed
socket can create an extremely troublesome parasitic
complementary bipolar process. The internal junction
network that can make it almost impossible to
breakdown voltages are relatively low for these very
achieve a smooth, stable frequency response. Best
small geometry devices. These breakdowns are
results are obtained by soldering the OPA659 directly
reflected in the Absolute Maximum Ratings table. All
onto the board.
device pins are protected with internal ESD protection
diodes to the power supplies, as Figure 39 shows.
f) The thermal slug on bottom of OPA659 DRB
package must be tied to the most negative
supply.
The
DRB
package
is
a
PowerPAD
thermally-enhanced
package.
Best
results
are
obtained by soldering the exposed metal tab on the
bottom of the OPA659 DRB directly to a metal plane
on the PCB that is connected to the most negative
supply voltage of the op amp. General layout
guidelines can be found in the application reports,
PowerPAD Layout
Guidelines (SLOA120)
and
PowerPAD Made Easy (SLMA004) , both available
Figure 39. Internal ESD Protection
for download from the TI web site at www.ti.com. It
may also be helpful to copy the EVM layout shown in
These diodes provide moderate protection to input
the Evaluation Module section.
overdrive voltages above the supplies as well. The
protection
diodes
can
typically
support
30mA
continuous
current.
Where
higher
currents
are
The DRB package option is a PowerPAD package
possible (for example, in systems with ±12V supply
that includes a thermal pad for increased thermal
parts driving into the OPA659), current limiting series
performance.
When
using
this
package,
it
is
resistors should be added into the two inputs. Keep
recommended to distribute the negative supply as a
these resistor values as low as possible because high
power plane, and tie the PowerPAD to this supply
values
degrade
both
noise
performance
and
with multiple vias for proper power dissipation. For
frequency response.
proper operation, the PowerPAD must be tied to the
most negative supply voltage. It is recommended to
use five evenly-spaced vias under the device as
18
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA659
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