SMART CARD SECTION (25 °C to +85°C ambient temperature, unless otherwise no" />
參數(shù)資料
型號： NCN6000DTBR2G
廠商： ON Semiconductor
文件頁數(shù)： 3/36頁
文件大?。?/td> 0K
描述： IC INTERFACE SMART CARD 20TSSOP
產(chǎn)品變化通告： Product Obsolescence 01/Jul/2009
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： ATM 終端，氣泵，ISM
接口： 微控制器
電源電壓： 2.7 V ~ 6 V
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 剪切帶 (CT)
安裝類型： 表面貼裝
其它名稱： NCN6000DTBR2GOSCT
NCN6000
http://onsemi.com
11
SMART CARD SECTION (25
°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
CRD_RST @ CRD_VCC = +5.0 V
Output RESET VOH @ Icrd_rst = 20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
CRD_RST @ Vcc = +3.0 V
Output RESET VOH @ Icrd_rst = 20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
VOH
VOL
tR
tF
VOH
VOL
tR
tF
12
CRD_VCC 0.9
0
CRD_VCC 0.9
0
CRD_VCC
0.4
100
CRD_VCC
0.4
100
V
ns
V
ns
CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V
CRD_VCC = +5.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50%
"1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = 20 mA
Output VOL @ Icrd_clk = 100 mA
CRD_VCC = +3.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50%
"1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = 20 mA @ Cout = 30 pF
Output VOL @ Icrd_clk = 100 mA @ Cout = 30 pF
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
13
45
3.15
0
40
1.85
0
5.0
55
18
CRD_VCC
+0.5
5.0
60
18
CRD_VCC
0.7
MHz
%
ns
V
MHz
%
ns
V
CRD_I/O @ CRD_VCC = +5.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = 20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
CRD_I/O @ CRD_VCC = +3.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = 20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
FIO
TRIO
TFIO
VOH
VOL
FIO
TRIO
TFIO
VOH
VOL
14
CRD_VCC 0.9
0
CRD_VCC 0.9
0
315
0.8
CRD_VCC
0.4
0.8
CRD_VCC
0.4
kHz
ms
V
kHz
ms
V
CRD_IO Pull Up Resistor @ PWR_ON = H
RCRDPU
14
20
26
k
W
Card Detection Debouncing Delay:
Card Insertion
Card Extraction
TCRDIN
TCRDOFF
11
50
150
ms
Card Insertion or Extraction Positive Going Input
High Voltage
VIHDET
11
0.70 * Vbat
Vbat
V
Card Insertion or Extraction Negative Going Input
Low Voltage
VILDET
11
0
0.30 * Vbat
V
Card Detection Bias Pull Up Current @
Vbat = 5.0 V
IDET
11
10
mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_iorst
12, 14
15
mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_clk
13
70
mA
8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over
the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.
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