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參數(shù)資料
| 型號： | MTB3N120E |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | JFETs |
| 英文描述： | 3 A, 1200 V, 5 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 322K |
| 代理商： | MTB3N120E |
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Capability Specified at Elevated Temperature
Low Stored Gate Charge for Efficient Switching
Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
Source–to–Drain Diode Recovery time Comparable to Discrete Fast Recovery Diode
*
See App. Note AN1327 – Very Wide Input Voltage Range; Off–line Flyback Switching Power Supply
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
1200
Vdc
Drain–Gate Voltage (RGS = 1.0 M)
VDGR
1200
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous @ 25
°C
Drain Current — Continuous @ 100
°C
Drain Current — Single Pulse (tp ≤ 10 s)
ID
IDM
3.0
2.2
11
Adc
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25
°C
Total Power Dissipation @ TA = 25°C (1)
PD
125
1.0
2.5
Watts
W/
°C
Watts
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 )
EAS
101
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB3N120E/D
Motorola, Inc. 1995
TMOS POWER FET
3.0 AMPERES
1200 VOLTS
RDS(on) = 5.0 OHM
CASE 418B–02, Style 2
D2PAK
Motorola Preferred Device
D
S
G
MTB3N120E
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