參數(shù)資料
型號(hào): MT93L00AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Multi-Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁(yè)數(shù): 8/39頁(yè)
文件大?。?/td> 636K
代理商: MT93L00AV
MT93L00A
Data Sheet
8
Zarlink Semiconductor Inc.
Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile.
A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following
condition:
Lsin > Lrin + 20log
10
(DTDT)
where DTDT is the Double-Talk
Detection Threshold.
Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted.
In G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk Detector
Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to get additional guardband, the DTDT is set
internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The MT93L00 allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT
(hex)
= hex(DTDT
(dec)
* 32768)
where 0 < DTDT
(dec)
< 1
Example:
For DTDT = 0.5625 (-5 dB), the
hexadecimal value becomes
hex(
0.5625 * 32768
)
= 4800h
Path Change Detector
Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned
on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon
detection of a major path change.
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