參數(shù)資料
型號(hào)： MT93L00AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： Multi-Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝： 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁(yè)數(shù)： 25/39頁(yè)
文件大?。?/td> 636K
代理商： MT93L00AV
MT93L00A
Data Sheet
25
Zarlink Semiconductor Inc.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
15
RP
14
RP
13
RP
12
RP
10
RP
9
RP
8
RP
11
Echo Canceller A, Rin Peak Detect Register 2 (RP)
Echo Canceller B, Rin Peak Detect Register 2 (RP)
Read Address: 0Dh + Base Address
Read Address: 2Dh + Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
7
RP
6
RP
5
RP
4
RP
2
RP
1
RP
0
RP
3
Echo Canceller A, Rin Peak Detect Register 1 (RP)
Echo Canceller B, Rin Peak Detect Register 1 (RP)
Read Address: 0Ch + Base Address
Read Address: 2Ch + Base Address
These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16 bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
15
SP
14
SP
13
SP
12
SP
10
SP
9
SP
8
SP
11
Echo Canceller A, Sin Peak Detect Register 2 (SP)
Echo Canceller B, Sin Peak Detect Register 2 (SP)
Read Address: 0Fh + Base Address
Read Address: 2Fh + Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
7
SP
6
SP
5
SP
4
SP
2
SP
1
SP
0
SP
3
Echo Canceller A, Sin Peak Detect Register 1 (SP)
Echo Canceller B, Sin Peak Detect Register 1 (SP)
Read Address: 0Eh + Base Address
Read Address: 2Eh + Base Address
These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16 bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
15
EP
14
EP
13
EP
12
EP
10
EP
9
EP
8
EP
11
Echo Canceller A, Error Peak Detect Register 2 (EP)
Echo Canceller B, Error Peak Detect Register 2 (EP)
Read Address: 11h + Base Address
Read Address: 31h + Base Address
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
7
EP
6
EP
5
EP
4
EP
2
EP
1
EP
0
EP
3
Echo Canceller A, Error Peak Detect Register 1 (EP)
Echo Canceller B, Error Peak Detect Register 1 (EP)
Read Address: 10h + Base Address
Read Address: 30h + Base Address
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16 bit 2’s complement
linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in
Register 1.
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