參數(shù)資料
型號： MT90883A
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 83/97頁
文件大?。?/td> 702K
代理商： MT90883A
MT90880/1/2/3
Data Sheet
83
Zarlink Semiconductor Inc.
10.0 AC Characteristics
10.1 WAN Access Interface
10.1.1 Slave Clock Mode
Table 31 - WAN Access Interface Timing - Slave Mode
Note 1:
In synchronous mode the clock must be within the locking range of the DPLL to function correctly (
±
245 ppm). In
asynchronous mode, the clock may be any frequency, provided there are 32 clocks between frame pulses (128 in 8.192 Mbs
mode)
Figure 38 - WAN Bus Slave Mode Timing at 2.048 Mbs
Data format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-bus 8.192 Mbs mode
WAN_CLKI frequency
f
C16P
16.384
MHz
Note 1
WAN_CLKI High Width
t
C16H
30
ns
WAN_CLKI Low Width
t
C16L
30
ns
ST-bus 2.048 Mbs mode
WAN_CLKI frequency
f
C4P
4.096
MHz
Note 1
WAN_CLKI High Width
t
C4H
122
ns
WAN_CLKI Low Width
t
C4L
122
ns
Generic E1 2.048 Mbs
mode
WAN_CLKI frequency
f
C2P
2.048
MHz
Note 1
WAN_CLKI High Width
t
C2H
244
ns
WAN_CLKI Low Width
t
C2L
244
ns
All modes
WAN_FRMI Setup Time
t
FOIS
5
ns
WAN_FRMI Hold Time
t
FOIH
5
ns
WAN_STO Delay
t
STOD
1
20
ns
WAN_STI Setup Time
t
STIS
5
ns
WAN_STI Hold Time
t
STIH
5
ns
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
B0
B7
Ch 31 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
tSTOD
tSTOD
tFOIH
tFOIS
tC4H
tC4L
tSTIH
tSTIS
tSTIH
tSTIS
WAN_CLKI
WAN_FRMI
WAN_STI
WAN_STO
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