參數(shù)資料
型號(hào)： MT90883A
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁(yè)數(shù)： 19/97頁(yè)
文件大?。?/td> 702K
代理商： MT90883A
MT90880/1/2/3
Data Sheet
19
Zarlink Semiconductor Inc.
Table 12 - Test Facilities
3.7.3 Test Operating Modes
1) Normal operating mode (T_MODE[1:0] = '11')
The device samples the T_D pins to determine the required operating mode shortly after reset is released.
These pins are known as the "bootstrap controls". The device has internal pull-up (100 K
±
30%) resistors
connected to the T_D bus pins. To pull-low connect a 10 K
pull-down resistor to ground. Bootstrap controls
are as follows:
Table 13 - Bootstrap Pin Functions
iddq
I
AD23
IDDQ test enable.
Set low for normal operation.
sclk_AT1
O
B26
Analog test output for system clock
PLL. Leave unconnected in normal
operation.
pclk_AT1
O
AF24
Analog test output for PCI clock PLL.
Leave unconnected in normal
operation.
ram_clk
O
Y2
66 MHz memory clock output.
This is used for test purposes only.
Leave unconnected in normal
operation.
T_D
Function
Notes
15
Reserved
14
Reserved
Pull low for normal operation.
13:11
Reserved
10:8
Selects delay of RAM_CLK output relative to
S_CLK.
Leave unconnected in normal operation.
7
Pull low to bypass PCI_CLK PLL.
Leave unconnected in normal operation.
6
Pull low to bypass the S_CLK PLL.
Leave unconnected in normal operation.
5
Controls m_mint0 and m_mint1 polarity - pull low
for active low and leave unconnected for active
high.
See Table 21.
4
Pull low to enable RAM_CLK output (otherwise it
will be high impedance).
Leave unconnected in normal operation.
3
Pull low for freeze enable.
Leave unconnected in normal operation.
2
Pull low for simulation speed-up.
This reduces the number of cycles that the chip is
held in reset after S_RST# and PCI_RST# have
gone high from 16348 to 256.
This should not be used during normal operation,
since the PLLs will not have time to lock.
Leave unconnected in normal operation.
0:1
Reserved
Signal
I/O
Width
Description
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